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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93CS40/41 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 and RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93CS40/TMP93CS41 Low Voltage/Low Power CMOS 16-Bit Microcontrollers TMP93CS40F/TMP93CS41F TMP93CS40DF/TMP93CS41DF 1. Outline and Device Characteristics The TMP93CS40/S41 are high-speed advanced 16-bit microcontrollers developed for controlling medium to large-scale equipment. The TMP93CS41 does not have a ROM; the TMP93CS40 has a built-in ROM. Otherwise, the devices function in the same way. The TMP93CS40/S41F are housed in a 100-pin flat package. The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) * * * * * TLCS-90 instruction mnemonic upward compatible 16-Mbyte linear address space General-purpose registers, register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions Micro DMA: 4 channels (1.6 s/2 bytes at 20 MHz) (2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal RAM: 2 Kbytes Internal ROM: TMP93CS40 TMP93CS41 64-Kbyte ROM None (4) External memory expansion * * * Can be expanded up to 16 Mbytes (for both programs and data). AM8/ 16 pin (selects the external data bus width) Can mix 8-/16-bit external data buses. ..... Dynamic bus sizing (5) 8-bit timer: 2 channels 030619EBP1 * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 93CS40-1 2004-02-10 TMP93CS40/TMP93CS41 (6) 8-bit PWM timer: 2 channels (7) 16-bit timer: 2 channels (8) 4-bit pattern generator: 2 channels (9) Serial interface: 2 channels (10) 10-bit AD converter: 8 channels (11) Watchdog timer (12) Chip select/wait controller: 3 blocks (13) Interrupt functions: 29 * * * 9 CPU interrupts .... SWI instruction, and illegal instruction 14 internal interrupts 6 external interrupts 7-level priority can be set. (14) I/O ports 79 pins for TMP93CS40 and 61 pins for TMP93CS41 (15) Standby function: 4 HALT modes (RUN, IDLE2, IDLE1, STOP) (16) Clock gear function * * * Dual clock operation Clock gear: High-frequency clock can be varied from fc to fc/16. Vcc = 2.7 to 5.5 V (17) Wide operating voltage (18) Package Type No. TMP93CS40F TMP93CS41F TMP93CS40DF TMP93CS41DF Package P-QFP100-1414-0.50 P-LQFP100-1414-0.50F 93CS40-2 2004-02-10 TMP93CS40/TMP93CS41 PA0 to PA6 PA7 (SCOUT) Port A 900/L CPU VCC [3] VSS [3] Highfrequency OSC X1 X2 CLK Lowfrequency OSC XT1 XT2 AM8/ AM16 EA RESET P50 to P57 (AN0 to AN7) AVCC AVSS VREFH VREFL 10-bit 8-ch AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR F PC (TXD0) P90 (RXD0) P91 (SCLK0/ CTS0 ) P92 (TXD1) P93 (RXD1) P94 (SCLK1) P95 Serial I/O (Channel 0) Serial I/O (Channel 1) ALE TEST1 TEST2 Interrupt controller P87 (INT0) NMI (PG00) P60 (PG01) P61 (PG02) P62 (PG03) P63 (PG10) P64 (PG11) P65 (PG12) P66 (PG13) P67 Pattern generator (Channel 0) Pattern generator (Channel 1) 2-Kbyte RAM Watchdog timer WDTOUT Port 0 P00 to P07 (AD0 to AD7) (TI0) P70 8-bit timer (Timer 0) 8-bit timer (Timer 1) Port 1 P10 to P17 (AD8 to AD15/A8 to A15) (TO1) P71 Port 2 P20 to P27 (A0 to A7/A16 to A23) (TO2) P72 8-bit PWM (Timer 2) 64-Kbyte ROM 8-bit PWM (Timer 3) P30 ( RD ) P31 ( WR ) P32 ( HWR ) Port 3 P33 ( WAIT ) P34 ( BUSRQ (TO3) P73 ) P35 ( BUSAK ) (INT4/TI4) P80 (INT5/TI5) P81 (TO4) P82 (TO5) P83 (INT6/TI6) P84 (INT7/TI7) P85 (TO6) P86 16-bit timer (Timer 4) 16-bit timer (Timer 5) (Not included on the TMP93CS41) CS/WAIT controller (3 blocks) P36 ( R/ W ) P37 ( RAS ) P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) P42 ( CS2 / CAS2 ) Figure 1.1 TMP93CS40/TMP93CS41 Block Diagram 93CS40-3 2004-02-10 TMP93CS40/TMP93CS41 2. Pin Assignment and Functions The assignment of input/output pins on the TMP93CS40/TMP93CS41, their names and outline functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment for the TMP93CS40F/S41F and TMP93CS40DF/S41DF. 88 P65/PG11 P66/PG12 P67/PG13 VSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC NMI 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 87 P64/PG10 86 P63/PG03 85 P62/PG02 84 P61/PG01 83 P60/PG00 82 P42/ CS2 / CAS2 81 P41/ CS1 / CAS1 80 P40/ CS0 / CAS0 79 P37/ RAS 78 P36/ R / W 77 P35/ BUSAK 76 P34/ BUSRQ 75 P33/ WAIT 74 P32/ HWR 73 P31/ WR 72 P30/ RD 71 P27/A7/A23 70 P26/A6/A22 69 P25/A5/A21 68 P24/A4/A20 67 P23/A3/A19 66 P22/A2/A18 ADC SIO P70/TI0 P71/TO1 P72/TO2 P73/TO3 P80/INT4/TI4 P81/INT5/TI5 P82/TO4 P83/TO5 P84/INT6/TI6 P85/INT7/TI7 P86/TO6 P87/INT0 P90/TXD0 P91/RXD0 P93/TXD1 P94/RXD1 P95/SCLK1 AM8/ AM16 CLK VCC VSS Timer Top view QFP100 (LQFP100) 65 64 63 62 60 59 58 57 56 55 54 P21/A1/A17 P20/A0/A16 VCC VSS P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 61 WDTOUT P92/ CTS0 /SCLK0 19 53 P10/AD8/A8 52 P07/AD7 51 P06/AD6 50 P05/AD5 49 P04/AD4 48 P03/AD3 47 P02/AD2 46 P01/AD1 45 P00/AD0 44 VCC 43 ALE 42 PA7/SCOUT 41 PA6 40 PA5 39 PA4 38 PA3 Clock mode X1 X2 EA RESET P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2 Note: Because the TMP93CS41 does not have an internal ROM, pins P00 to P17 are tied to AD0 to AD15 (when AM8/ AM16 = 0), or to AD0 to AD7 and A8 to A15 (when AM8/ AM16 = 1). P30 is tied to RD , P31 to WR . Figure 2.1.1 Pin Assignment (100-Pin QFP and 100-Pin LQFP) 93CS40-4 2004-02-10 Memory interface Stepping motor control Programmable Pull Pull up down TMP93CS40 Pin no. Pin no. TMP93CS40 Programmable Pull Pull down up TMP93CS40/TMP93CS41 2.2 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 to Table 2.2.4 show pin names and functions. Table 2.2.1 Pin Names and Functions (1/4) Pin Names P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O I/O Tri-state I/O Tri-state Output I/O Output Output Functions Port 0: I/O port that allows at the bit level Address/data (lower): Bits 0 to 7 of address/data bus Port 1: I/O port that allows at the bit level Address data (upper): Bits 8 to 15 of address/data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows selection of I/O at the bit level (with pull-down resistor) Address: bits 0 to 7 of address bus Address: bits 16 to 23 of address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data on pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to AD15 Port 33: I/O port (with pull-up resistor) Wait: in used to request CPU bus wait Port 34: I/O port (with pull-up resistor) Bus request: Signal used to request bus release Port 35: I/O port (with pull-up resistor) Bus acknowledge: Signal used to acknowledge bus release Port 36: I/O port (with pull-up resistor) Read/write: 1 represents read or dummy cycle; 0 represents write cycle. Port 37: I/O port (with pull-up resistor) Row address strobe: Outputs RAS strobe for DRAM. Port 40: I/O port (with pull-up resistor) Chip select 0: Outputs 0 when address is within specified address area. Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area. 8 1 1 1 1 1 1 1 1 1 Output Output Output Output I/O Output I/O Input I/O Input I/O Output I/O Output I/O Output I/O Output Output P31 WR P32 HWR P33 WAIT P34 BUSRQ P35 BUSAK P36 R/ W P37 RAS P40 CS0 CAS0 Note: This device's built-in memory or built-in I/O cannot be accessed by an external DMA controller using the BUSRQ and BUSAK signals. 93CS40-5 2004-02-10 TMP93CS40/TMP93CS41 Table 2.2.2 Pin Names and Functions (2/4) Pin Names P41 CS1 CAS1 Number of Pins 1 I/O I/O Output Output Functions Port 41: I/O port (with pull-up resistor) Chip select 1: Outputs 0 if address is within specified address area. Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area. Port 42: I/O port (with pull-down resistor) Chip select 2: Outputs 0 if address is within specified address area. Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area. Port 5: Input port Analog input: Analog signal input for AD converter Pin for high level reference voltage input to AD converter Pin for low level reference voltage input to AD converter Ports 60 to 63: I/O ports that allow selection of I/O at the bit level (with pull-up resistor) Pattern generator ports: 00 to 03 Ports 64 to 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor) Pattern generator ports: 10 to 13 Port 70: I/O port (with pull-up resistor) Timer input 0: Timer 0 input Port 71: I/O port (with pull-up resistor) Timer output 1: Timer 0 or timer 1 output Port 72: I/O port (with pull-up resistor) PWM output 2: 8-bit PWM timer 2 output Port 73: I/O port (with pull-up resistor) PWM output 3: 8-bit PWM timer 3 output Port 80: I/O port (with pull-up resistor) Timer input 4: Timer 4 count/capture trigger signal input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 81: I/O port (with pull-up resistor) Timer input 5: Timer 5 count/capture trigger signal input Interrupt request pin 5: Interrupt request pin with rising edge Port 82: I/O port (with pull-up resistor) Timer output 4: Timer 4 output pin Port 83: I/O port (with pull-up resistor) Timer output 5: Timer 4 output pin P42 CS2 CAS2 1 I/O Output Output P50 to P57 AN0 to AN7 VREFH VREFL P60 to P63 PG00 to PG03 P64 to P67 PG10 to PG13 P70 TI0 P71 TO1 P72 TO2 P73 TO3 P80 TI4 INT4 P81 TI5 INT5 P82 TO4 P83 TO5 8 1 1 4 Input Input Input Input I/O Output 4 I/O Output 1 1 1 1 1 I/O Input I/O Output I/O Output I/O Output I/O Input Input 1 I/O Input Input 1 1 I/O Output I/O Output 93CS40-6 2004-02-10 TMP93CS40/TMP93CS41 Table 2.2.3 Pin Names and Functions (3/4) Pin Names P84 TI6 INT6 P85 TI7 INT7 P86 TO6 P87 INT0 P90 TXD0 P91 RXD0 P92 CTS0 Number of Pins 1 I/O I/O Input Input Functions Port 84: I/O port (with pull-up resistor) Timer input 6: Timer 5 count/capture trigger signal input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Port 85: I/O port (with pull-up resistor) Timer input 7: Timer 5 count/capture trigger signal input Interrupt request pin 7: Interrupt request pin with rising edge Port 86: I/O port (with pull-up resistor) Timer output 6: Timer 5 output pin Port 87: I/O port (with pull-up resistor) Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Port 90: I/O port (with pull-up resistor) Serial data send 0 Port 91: I/O port (with pull-up resistor) Serial data receive 0 Port 92: I/O port (with pull-up resistor) Serial data send enable 0 (Clear to send) Serial Clock I/O 0 Port 93: I/O port (with pull-up resistor) Serial data send 1 Port 94: I/O port (with pull-up resistor) Serial data receive 1 Port 95: I/O port (with pull-up resistor) Serial clock I/O 1 Ports A0 to A6: I/O ports Port A7: I/O port System clock output: Outputs fFPH or fSYS clock. Watchdog timer output pin Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge or with both edges programmable. Clock output: Outputs [fSYS / 2] clock. Pulled-up during reset. Can be disabled to reduce noise. 1 I/O Input Input 1 1 1 1 1 I/O Output I/O Input I/O Output I/O Input I/O Input I/O SCLK0 P93 TXD1 P94 RXD1 P95 SCLK1 PA0 to PA6 PA7 SCOUT WDTOUT NMI 1 1 1 7 1 1 1 1 I/O Output I/O Input I/O I/O I/O I/O Output Output Input Output CLK EA 1 Input External access: On the TMP93CS41, the Vss pin should be connected. On the TMP93CS40, the Vcc pin should be connected. 93CS40-7 2004-02-10 TMP93CS40/TMP93CS41 Table 2.2.4 Pin Names and Functions (4/4) Pin Names AM8/ AM16 Number of Pins 1 I/O Input (On the TMP93CS40) Functions Address mode: Selects external data bus width. The Vcc pin should be connected. The data bus width for external access is set by the chip select/WAIT control register, port 1 control register. (On the TMP93CS41) The Vss pin should be connected to access either fixed 16-bit bus width, or 16-bit bus interchangeable with 8-bit bus. The Vcc pin should be connected to access a fixed 8-bit bus width. ALE RESET 1 1 2 1 1 2 3 3 1 1 Output Input I/O I/O Input I/O Output Output/Input Address latch enable (Can be disabled to reduce noise.) Reset: Initializes TMP93CS40/TMP93CS41. (with pull-up resistor) High-frequency oscillator connecting pin Port 96: I/O port (open-drain output) Low-frequency oscillator connecting pin Port 97: I/O port (open drain output) Low-frequency oscillator connecting pin TEST1 pin should be connected to TEST2 pin. Don't connect to any other pins. Power supply pin (All VCC pins should be connected to the power supply pin.) GND pin (0 V) (All VSS pins should be connected to GND (0 V).) Power supply pin for AD converter GND pin for AD converter (0 V) X1/X2 P96 XT1 P97 XT2 TEST1/TEST2 VCC VSS AVCC AVSS Note: All pins that have built-in pull-up/pull-down resistors (other than the RESET pin) can be disconnected from the built-in pull-up/pull-down resistor by software. 93CS40-8 2004-02-10 TMP93CS40/TMP93CS41 3. Operation This section describes in blocks the functions and basic operations of TMP93CS40 and TMP93CS41 devices. Please also refer to section 7. Precautions in use, which describes some points requiring careful attention. 3.1 CPU TMP93CS40 and TMP93CS41 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For basics of the CPU operation, see the information on the TLCS-900/L CPU in the previous chapter.) This section describes some CPU functions unique to the TMP93CS40 and TMP93CS41, that are not described in the previous chapter, entitled TLCS-900/L CPU. 3.1.1 Reset When resetting the TMP93CS40 and TMP93CS41 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (16 s at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 x 1/2). * When a reset signal is accepted, the CPU sets itself as follows: The program counter (PC) is set according to the reset vector that is stored from 8000H to 8002H. PC<7:0> Data in location 8000H PC<15:8> Data in location 8001H * * * * PC<23:16> Data in location 8002H The stack pointer (XSP) for system mode is set to 100H. The The Note 1: Resetting makes no change in any register in the CPU except the program counter (PC), status register (SR) and stack pointer (XSP), nor in the data in the internal RAM. Note 2: The CLK pin is pulled up during reset. When the voltage is externally reduced, there is a possibility of causing malfunctions. Figure 3.1.1 and Figure 3.1.2 show the reset timing chart of the TMP93CS41 and TMP93CS40. 93CS40-9 2004-02-10 45 X1 cycles omitted Total of 220 X1 cycles omitted X1 Sampling Sampling (P20 to P27 input mode) (P40 to P41 input mode) CLK RESET A16 to A23 CS0 to CS1 (P42 input mode) (P36 input mode) CS2 R/W ALE Address Address Address Data input AD0 to AD15 RD Read AD0 to AD15 Address Data output Address (Starts read cycle of 2 waits after reset release) Write (P32 input mode) (P37 input mode) (P40 to P41 input mode) (P42 input mode) (Input mode) (Input mode) (Input mode) (Output mode: Open-drain output) Figure 3.1.1 TMP93CS41 Reset Timing Chart 93CS40-10 WR HWR RAS CAS0 to CAS1 CAS2 P20 to P27, P42 P32 to P37, P40 to P41 P60 to P67, P70 to P73 P80 to P87, P90 to P95 P50 to P57, PA0 to PA7 P96 to P97 TMP93CS40/TMP93CS41 2004-02-10 Internal pull up or pull down High impedance 45 X1 cycles omitted Total of 220 X1 cycles omitted X1 Sampling Sampling (P20 to P27 input mode) (P40 to P41 input mode) CLK RESET A16 to A23 CS0 to CS1 (P42 input mode) (P36 input mode) CS2 R/W ALE Address Address AD0 to AD15 Read RD Address Data output Address AD0 to AD15 (Starts read cycle of 2 waits after reset release) Write (P32 input mode) (P37 input mode) (P40 to P41 input mode) (P42 input mode) (Input mode) (Input mode) (Input mode) (Output mode: Open-drain output) Figure 3.1.2 TMP93CS40 Reset Timing Chart 93CS40-11 WR HWR RAS CAS0 to CAS1 CAS2 P20 to P27, P42 P32 to P37, P40 to P41 P60 to P67, P70 to P73 P80 to P87, P90 to P95 P50 to P57, PA0 to PA7 P96 to P97 TMP93CS40/TMP93CS41 2004-02-10 Internal pull up or pull down High impedance TMP93CS40/TMP93CS41 3.1.2 AM8/ AM16 Pin (1) TMP93CS40 Set this pin to 1. Resetting accesses a built-in ROM via the internal 16-bit bus. When accessing externally, the bus width is set by the chip select/wait control register described in 3.6.3, and the registers of port 1. (2) TMP93CS41 1. With fixed 16-bit data bus or with 16-bit data bus interchangeable with 8-bit data bus. Set this pin to 0. Port 1, AD8 to AD15 or A8 to A15 pins are fixed to AD8 to AD15 functions. Any values set in the port 1 control register or the port 1 function register are invalid. The external data bus width is set by the chip select/wait control register. After reset, it is necessary to set the program memory to be accessed, to 16-bit data bus. With fixed external 8-bit data bus Set this pin to 1. Port 1, AD8 to AD15 or A8 to A15 pins are fixed to A8 to A15 functions. Any values set in the port 1 control register or the port 1 function register are invalid. The values of Bit4 2. 93CS40-12 2004-02-10 TMP93CS40/TMP93CS41 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP93CS40 and TMP93CS41. 000000H Internal I/O (128 bytes) 000080H 256-byte direct area (n) 000100H Internal RAM (2 Kbytes) 000880H External memory 64-Kbyte area (nn) 008000H 008100H Interrupt vector table area (64 entries x 4 bytes) 010000H 64-Kbyte internal ROM (TMP93CS40) External memory area in TMP93CS41 018000H External memory 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Reserved (256 bytes) ( = Internal area) Note: The 256-byte area from FFFF00H to FFFFFFH can not be used. Figure 3.2.1 Memory Map 93CS40-13 2004-02-10 TMP93CS40/TMP93CS41 3.3 Dual Clock, Standby Function Dual clock, standby control circuits are comprised of a system clock controller, prescaler clock controller, internal clock pin output function and standby controller. The oscillator operating modes are classified as either (a) Single clock mode (using only the X1 and X2 pins), or (b) Dual clock mode (using the X1, X2, XT1, and XT2 pins). Figure 3.3.1 shows state diagrams for the two clock modes. Figure 3.3.2 shows the corresponding block diagram, Figure 3.3.3 displays functions of the I/O registers and Table 3.3.1 lists correspondences between alternative states of the system clock and those of the CPU, oscillator and internal I/O components. RESET RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) IDLE1 mode (Operates only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fc/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) (a) Single Clock Mode State Diagram RESET RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) IDLE 1 mode (Operates only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fc/gear value/2) Instruction Instruction Interrupt STOP mode (Stops all circuits) RUN mode (Stops only CPU) IDLE 2 mode (Stops CPU and AD) IDLE 1 mode (Operates only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction SLOW mode (fs/2) (b) Dual Clock Mode State Diagram Figure 3.3.1 State Diagrams The clock frequency input from the X1 and X2 pins is called fc, and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 93CS40-14 2004-02-10 TMP93CS40/TMP93CS41 Table 3.3.1 Relations between System Clock States and Other Internal Operations Operating Mode RESET Single clock NORMAL RUN IDLE2 IDLE1 STOP RESET NORMAL Dual clock SLOW RUN IDLE2 IDLE1 STOP Oscillation Stop Stop Programmable Oscillation Stop only AD Stop Reset Oscillation Stop Stop Oscillator High Low Frequency (fc) Frequency (fs) CPU Reset Operate Internal I/O Reset Operate Stop only AD Stop Reset System Clock fSYS fc/32 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32) Stop fc/32 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32) fs/2 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32, fs/2) Stop Operate Operate Programmable Oscillator being used as system clock: Oscillation Other oscillator: Programmable Stop Stop 93CS40-15 2004-02-10 * Warm-up (Changing clocks) ... fc or fs. * Warm-up (Releasing STOP mode) ... fFPH SYSCR0 8-bit pWMs 0 and 1 5-bit prescaler Run and stop TRUN Figure 3.3.2 Block Diagram of Dual Clock and Standby Circuits SYSCR0 93CS40-16 fFPH System clock fSYS Internal I/O ROM, RAM SYSCR0 XT2 XT1 Low-frequency oscillator /2 CPU Selector /2 Selector CLK SCOUT/PA7 WDMOD SYSCR1 SYSCR0 fc/2 fc/4 fc/8 fc/16 X2 /2 /4 /8 /16 TMP93CS40/TMP93CS41 2004-02-10 X1 High-frequency oscillator fc CKOCR TMP93CS40/TMP93CS41 7 SYSCR0 (006EH) 6 XTEN 0 Lowfrequency oscillator (fs) 0: Stop 1: Oscillation 5 RXEN 1 Highfrequency oscillator (fc) after released STOP mode 0: Stop 1: Oscillation 4 RXTEN R/W 0 Lowfrequency oscillator (fs) after released STOP mode 0: Stop 1: Oscillation 3 RSYSCK 0 Select clock after STOP mode is released 0: fc 1: fs 2 WUEF 0 Warm-up timer (Write) 0:Don't care 1: Start timer (Read) 0: Warm up complete 1: Continue warm up 1 PRCK1 0 00: fFPH 01: fs 10: fc/16 11: (Reserved) 0 PRCK0 0 Bit symbol Read/Write After reset Function XEN 1 Highfrequency oscillator (fc) 0: Stop 1: Oscillation Select prescaler clock SYSCR1 (006FH) Bit symbol Read/Write After reset Function SYSCK 0 Select system clock 0: fc 1: fs GEAR2 R/W GEAR1 GEAR0 1 0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) HALTM0 0 RESCR 0 1: Connects WDT output to reset pin internally. WDMOD (005CH) Bit symbol Read/Write After reset Function WDTE 1 WDT control 1: Enable WDTP1 0 WDTP0 0 WARM R/W 0 Warm-up timer 14 0: 2 / frequency input 16 1: 2 / frequency input HALTM1 0 Standby mode 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE mode DRVE 0 1: Drives pin even in STOP mode WDT detection time 00: 2 /fSYS 01: 2 /fSYS 10: 219/fSYS 11: 221/fSYS 17 15 CKOCR (006DH) Bit symbol Read/Write After reset Function SCOSE 0 SCOUT select 0: fFPH 1: fSYS SCOEN R/W 0 SCOUT output control 0: I/O port 1: SCOUT output ALEEN 0/1 (Note 2) ALE pin output control 0: HZ port 1: ALE output CLKEN 0/1 (Note 2) CLK pin output control 0: HZ port 1: CLK output Note 1: Note 2: SYSCR1 Note 3: Figure 3.3.3 I/O Register about Dual Clock, Standby 93CS40-17 2004-02-10 TMP93CS40/TMP93CS41 3.3.1 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high frequency (fc). The register SYSCR1 High-frequency clock X1 X2 X1 X2 XT1 Low-frequency clock XT2 XT1 XT2 (Open) 74HCU04 * See application circuit in chapter 5. (a) Crystal/ceramic resonator (b) External oscillator (c) Crystal resonator (b) External oscillator Figure 3.3.4 Examples of Resonator Connection Note 1: Note on using the low-frequency oscillation circuit. In connecting the low-frequency resonator to ports 96 and 97, it is necessary to make the following settings to reduce the power consumption. (Connecting with resonators) P9CR 93CS40-18 2004-02-10 TMP93CS40/TMP93CS41 (1) Switching from NORMAL to SLOW mode When the resonator is connected to the X1 and X2, or to the XT1 and XT2 pins, the warm-up timer is used to change the operation frequency after stable oscillation is attained. The warm-up time can be selected by WDMOD 0 (214/frequency) 1 (216/frequency) Change to NORMAL (fc) 0.8192 ms 3.2768 ms Change to SLOW (fs) 500 ms 2000 ms at fc = 20 MHz, fs = 32.768 kHz 93CS40-19 2004-02-10 TMP93CS40/TMP93CS41 Clock setting example 1: Changing from high frequency (fc) to low frequency (fs). SYSCR0 SYSCR1 WDCR WDMOD EQU EQU EQU EQU RES LD SET SET SET WUP: BIT JR SET RES SET 006EH 006FH 005DH 005CH 7, (WDMOD) (WDCR), B1H 4, (WDMOD) 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) 7, (WDMOD) ; ; Disables watchdog timer. ; Sets warm-up time to 216/fs. ; Enables low-frequency oscillation. ; Clears and starts warm-up timer. ; ; Detects stopping of the warm-up timer. ; Changes fSYS from fc to fs. ; Disables high-frequency oscillation. ; Enables watchdog timer. Enables low frequency Clears and starts warm-up timer Changes fSYS Disables high frequency from fc to fs Stopping of warm-up timer 93CS40-20 2004-02-10 TMP93CS40/TMP93CS41 Clock setting example 2: Changing from low frequency (fs) to high frequency (fc). SYSCR0 SYSCR1 WDCR WDMOD EQU EQU EQU EQU RES LD RES SET SET WUP: BIT JR RES RES SET 006EH 006FH 005DH 005CH 7, (WDMOD) (WDCR), B1H 4, (WDMOD) 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) 7, (WDMOD) ; ; Disables watchdog timer. ; Sets warm-up time to 214/fc. ; Enables high-frequency oscillation (fc). ; Clears and starts warm-up timer. ; ; Detects stopping of the warm-up timer. ; Changes fSYS from fs to fc. ; Disables low-frequency oscillation. ; Enables watchdog timer. Enables high frequency Clears and starts warm-up timer 93CS40-21 2004-02-10 TMP93CS40/TMP93CS41 (2) Clock gear controller When the high-frequency clock fc is selected at SYSCR1 SYSCR1 EQU 006FH ; Changes fSYS to fc/2. LD (SYSCR1), XXXX0000B X: Don't care (High-frequency clock gear changing) To change the frequency of the clock gear, write the value to the SYSCR1 SYSCR1 EQU 006FH LD (SYSCR1), XXXX0001B LD (DUMMY), 00H ; Changes fSYS to fc/4. ; Dummy instruction. Instruction to be executed by the clock gear after changing. 93CS40-22 2004-02-10 TMP93CS40/TMP93CS41 3.3.2 Prescaler Clock Controller The 9-bit prescaler provides a clock signal to the 8-bit timer 0 and timer 1, 16-bit timer 4 and timer 5, and serial interface 0 and serial interface 1. The 5-bit prescaler provides a clock signal to the 8-bit PWM timer 0 and 1. The clock input to the 5-bit prescaler is a clock signal which is selected as either fFPH, fc/16, or fs according to the value in the SYSCR0 3.3.3 Internal Clock Pin Output Function (1) PA7/SCOUT pin The PA7/SCOUT pin outputs the internal clock signals fFPH or fSYS. One bit in the port A control register PACR fFPH fSYS NORMAL, SLOW Outputs fFPH clock. Outputs fSYS clock. HALT Mode RUN, IDLE2, IDLE1 STOP Fixed to 0 or 1. 93CS40-23 2004-02-10 TMP93CS40/TMP93CS41 (2) CLK pin The CLK pin outputs the internal clock signal fSYS divided by 2. The type of output is determined by one bit in the clock output control register, CKOCR TMP93CS40 TMP93CS41 CKOCR 0 1 CLK Pin Operation High impedance fSYS/2 clock output Note: To set CKOCR 93CS40-24 2004-02-10 TMP93CS40/TMP93CS41 3.3.4 Standby Controller (1) HALT mode When the HALT instruction is executed, the operating mode changes to RUN, IDLE2, IDLE1 or STOP mode depending on the contents of the HALT mode setting register WDMOD WDMOD Bit symbol (005CH) Read/Write After reset Function WDTE 1 Watchdog timer control 0: Disable 1: Enable 6 WDTP1 0 5 WDTP0 0 4 WARM 0 Warm-up timer 0: 214/clock frequency selection 1: 216/clock frequency selection 3 HALTM1 R/W 0 2 HALTM0 0 1 RESCR 0 0 DRVE 0 Watchdog timer detect time selection 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 2 /fSYS 21 HALT mode selection 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode Runaway STOP mode detection pin control internal 1: Drive pins reset control in STOP 1: Executes mode internal reset by runaway detection Pin state control in STOP mode 0 1 I/O off Retains the state before HALT HALT mode setting 00 RUN mode (only CPU stops) 01 STOP mode (all circuits stop) 10 IDLE1 mode (only oscillator operating) 11 IDLE2 mode (partial I/O operation) Warm-up time selection at returning from the STOP mode (see table 3.3.7) 0 1 214/select clock frequency 216/select clock frequency Figure 3.3.5 Watchdog Timer Mode Register The features of the RUN, IDLE2, IDLE1, and STOP modes are as follows. 1. RUN: Only the CPU HALTs. 2. IDLE2: The built-in oscillator and the specified I/O operates. 3. IDLE1: Only the built-in oscillator operates, while all other built-in circuits stop. 4. STOP: All internal circuits including the built-in oscillator stop. This greatly reduces power consumption. The operations in the halt state are described in Table 3.3.5. 93CS40-25 2004-02-10 TMP93CS40/TMP93CS41 Table 3.3.5 I/O Operation during HALT Mode HALT mode WDMOD RUN 00 IDLE2 11 HALT IDLE1 10 STOP 01 Maintain the state when the HALT instruction was executed. See Table 3.3.8 (2) How to release the HALT mode These halt states can be released by resetting or by requesting an interrupt. The halt release sources are determined by the combinations between the states of the interrupt mask register * 93CS40-26 2004-02-10 TMP93CS40/TMP93CS41 When releasing the HALT mode by resetting, the internal RAM data keeps the state before the "HALT" instruction is executed. However the other setting contents are initialized (Releasing due to interrupts keep the state before the "HALT" instruction is executed.) When the HALT mode is released by resetting, the internal RAM data maintains the state it was in before the HALT instruction was executed. However the other setting contents are initialized. (Release of the HALT mode due to interrupts maintains all setting contents in their states before the HALT instruction was executed.) Table 3.3.6 Halt Release Sources and Halt Release Operations Interrupt Receiving Status HALT Mode Halt release source Interrupt NMI INTWDT INT0 INT4 to INT7 INTT0 to INTT3 INTTR4 to INTTR7 INTRX0, TX0 INTRX1, TX1 INTAD RESET Interrupt Enabled (Interrupt level) (Interrupt mask) Interrupt Disabled (Interrupt level) < (Interrupt mask) RUN IDLE2 IDLE1 STOP x x x x x x x x x x x x x x x x *1 *1 RUN - - IDLE2 IDLE1 STOP - - - - - - x x x x x x x x x x x x x x x x x x *1 x x x x x x : After release of the HALT mode, the CPU starts interrupt processing. (RESET initializes LSI.) : After release of the HALT mode, the CPU starts executing the next instruction that follows the HALT instruction. x: Cannot be used to release the HALT mode. -: This combination type does not exist because the priority level (Interrupt request level) of non-maskable interrupts is fixed to the highest priority level 7. *1: Release the HALT mode is executed after the warm-up cycle is completed. Note: When release of the HALT mode is executed by an INT0 interrupt of the level mode in the interrupt enabled status, maintain level H until the start of interrupt processing. If level L is set before the start of interrupt processing, interrupt processing is correctly started. Example of releasing the RUN mode: An INT0 interrupt releases the halt state when the RUN mode is on. Address 8203H 8206H 8209H 820BH 820EH INT0 LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (WDMOD), 00H ; Select interrupt rising edge. ; Sets interrupt level to 6 for INT0. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to run. ; Halts CPU. INT0 interrupt routine 820FH LD XX, XX RETI 93CS40-27 2004-02-10 TMP93CS40/TMP93CS41 (3) Operation 1. RUN mode In the RUN mode, the system clock in the MCU continues to operate even after a HALT instruction is executed. Only the CPU stops executing further instructions. In the halt state, an interrupt request is accepted on the falling edge of the CLK signal. Release of the RUN mode is executed by the external or internal interrupts. (See Table 3.3.6 "Halt Release Sources and Halt Release Operations".) Figure 3.3.6 shows the timing for releasing the halt state by interrupts in the RUN or IDLE2 modes. X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Address + 2 Address Data Address Address Data INT0 (Level) INT4 to INT7 (Rising edge) INT4, INT6 (Falling edge) Internal INT RUN or IDLE2 modes Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2 Modes 2. IDLE2 mode In the IDLE2 mode, the system clock signal is supplied only to specific internal I/O devices, and the CPU stops executing the current instruction. In the IDLE2 mode, the halt state is released by an interrupt with the same timing as in the RUN mode. The IDLE2 mode is released by external or internal interrupts, except for INTWDT and INTAD interrupts. (See Table 3.3.6 "Halt Release Sources and Halt Release Operations".) In the IDLE2 mode, the watchdog timer should be disabled before entering the halt status, to prevent the watchdog timer interrupt from occurring just after release of the HALT mode. 93CS40-28 2004-02-10 TMP93CS40/TMP93CS41 3. IDLE1 mode In the IDLE1 mode, only the internal oscillator operates. The system clock in the MCU stops, and the CLK pin is fixed at the level H in the output enabled state. (CKOCR X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Address + 2 Address Data Address Data INT0 (Level) INT0 (Rising edge) IDLE1 mode Figure 3.3.7 Timing Chart of Halt State Release by Interrupts in IDLE1 Mode 93CS40-29 2004-02-10 TMP93CS40/TMP93CS41 4. STOP mode The STOP mode is selected to stop all internal circuits including the internal oscillator. The pin status in the STOP mode depends on the setting of a bit in the watchdog timer mode register WDMOD Warm-up time X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Address + 2 Address Data Address Data INT0 (Level) INT0 (Rising edge) STOP mode Figure 3.3.8 Timing Chart of Halt State Release by Interrupts in STOP Mode Table 3.3.7 Example of Warm-up Time after Releasing the STOP Mode Clock Operation Frequency after the STOP Mode is Released fc fc/2 fc/4 fc/8 fc/16 fs Warm-up Time [ms] WDMOD 0.8192 1.6384 3.2768 6.5536 13.1072 500 3.2768 6.5536 13.1072 26.2144 52.4288 2000 Clock Frequency fc = 20 MHz fs = 32.768 kHz 93CS40-30 2004-02-10 TMP93CS40/TMP93CS41 How to calculate the warm-up time WDMOD Address SYSCR0 SYSCR1 WDMOD 8FFDH 9000H 9002H 9005H NMI EQU EQU EQU LD RES LD HALT 006EH 006FH 005CH (SYSCR1), 08H 4,(WDMOD) (SYSCR0), -11000 - - B ; fSYS = fs/2. ; Sets warm-up time to 214/fc. ; Operates at high frequency after STOP mode is released. Clears and starts warm-up timer (High frequency) End NMI interrupt routine 9006H LD -: No change XX, XX RETI Note: When different operation modes are used before and after the STOP mode, and halt release interrupt request is accepted during execution of the HALT instruction (8 states), it is possible to release the HALT mode without changing the operation mode. In a system which accepts interrupts during execution of the HALT instruction, set the same operation mode before and after the STOP mode. 93CS40-31 2004-02-10 TMP93CS40/TMP93CS41 Table 3.3.8 Pin States in STOP Mode Pin name P00 to P07 Input mode Output mode AD8 to AD15 Input mode Output mode AD0 to AD7 Input mode Output mode, A0 to A7/A16 to A23 Output Input mode Output mode Input mode Output mode Input mode Output mode Input mode Input mode Output mode Input mode Output mode Input mode Output mode Input mode Output mode Input mode (INT0) Input mode Output mode Input mode Output mode Input mode Output mode, SCOUT Input Output Output ( I/O TMP93CS40 - - - - - PU* PU* PU* PU* PD* PD* PU* PU* PU* PU* PU* PU* PU PU Input PU* PU* - - - - Input Output "L" - Input Input Input - "H" - - - - - - TMP93CS41 - Output - Output - Output Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Input Output Input Output Input Output Input Output "L" "H" Input Input Input - "H" Input Output* - Input Output* - - P10 to P17 x x - - x x - Output "H" P20 to P27 P30 ( RD ), P31 ( WR ) P32 to P37 P40, P41 P42 (CS2/CAS2) P5 P6 P7 P80 to P86 P87 (INT0) P90 to P95 PA0 to PA6 PA7 NMI The same as for TMP93CS40 WDOUT ALE CLK RESET EA AM8/ AM16 X1 X2 P96 P97 (Align) -: Input: Output: Output*: PU: PU*: PD*: : x: Input is not accepted; output is at high impedance. Input gate in operation. Fix input voltage to "L" or "H" so that the input state pin stays constant. Output state. Open-drain output state. Input gate in operation. Set output to "L" or attach pull up on pin so that the input gate stays constant. Programmable pull-up pin. When a pull-up resistor is not set, fix the pin to avoid through current because the input gate always operates. Programmable pull-up pin in input gate disable state. No through current flows even if the pin is set to high impedance. Programmable pull-down pin in input gate disable state. No through current flows even if the pin is set to high impedance. When a HALT instruction is executed and CPU stops at the address of the port register, an input gate operates. Fix the pin to avoid through current, and change the program. In all other cases, input is not accepted; output is at high impedance. Cannot be set. 93CS40-32 2004-02-10 TMP93CS40/TMP93CS41 Note: Port registers are used for controlling programmable pull up/pull down. If a pin can be used for an output function (e.g., P71/TO1) and the output function is specified, whether pull up or pull down is selected depends on the output function data. If a pin can be used for an input function, whether pull up or pull down is selected depends on the port register setting value only. 93CS40-33 2004-02-10 TMP93CS40/TMP93CS41 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register SR A fixed individual interrupt vector number is assigned to each interrupt source; any one of six levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority of 7. When an interrupt is generated, the interrupt controller sends the value of the priority of the interrupt source to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the highest) to the CPU. The CPU compares the value of the priority sent, with the value in the CPU interrupt mask register 93CS40-34 2004-02-10 TMP93CS40/TMP93CS41 Interrupt processing Read interrupt vector V. Clear interrupt request flag. Internal operation Vector V = Micro DMA start vector? No Yes Data transfer by micro DMA General-purpose interrupt processing PUSH PC PUSH SR SR Count Count - 1 Micro DMA processing (Note) Yes Count = 0? No PC (8000H + V) Interrupt processing program User program RETI instruction POP SR POP PC INTNEST INTNEST - 1 Note: In read-only mode, always branches to No without conditional branch. End Figure 3.4.1 Interrupt Processing Flowchart 93CS40-35 2004-02-10 TMP93CS40/TMP93CS41 3.4.1 General-purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows. In the cases of software interrupts or interrupts generated by the CPU because of attempts to execute illegal instructions, the following steps (1) and (3) are not executed. (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority, then clears the interrupt request. The default priority is fixed as follows: The smaller the vector value, the higher the priority. (2) The CPU pushes the program counter and the status register to the system stack area (Area indicated by the system mode stack pointer (XSP)). (3) The CPU sets a value in the CPU interrupt mask register 8 bits 16 bits Bus Width of Interrupt Vector Area 8 bits 16 bits 8 bits 16 bits Number of Interrupt Processing States Max Mode 35 31 29 25 Min Mode 31 27 27 23 The RETI instruction is usually used to complete the interrupt processing. Executing this instruction restores the contents of the program counter and the status registers, and decrements the interrupt nesting counter (INTNEST). Though acceptance of non-maskable interrupts cannot be disabled by programming, acceptance of maskable interrupts can. A priority can be set for each source of maskable interrupts. The CPU accepts any interrupt request with a priority higher than the current value in the CPU mask register 93CS40-36 2004-02-10 TMP93CS40/TMP93CS41 (1) Maskable interrupt (main) EI 1 [1] INTT0 (Level 1) [5] [4] IFF1 RETI IFF2 [2] (INTT0 interrupt routine) (2) Non-maskable interrupt (main) (NMI routine) DI [1] NMI IFF7 [2] [3] (Level 7) [5] [4] IFF7 [3] RETI During execution of the main program, the CPU accepts an interrupt request. The CPU then increments IFF so that no new interrupts of priority level 1 will be accepted during processing of the interrupt routine. The DI instruction is executed in the main program, so that only interrupts of priority level 7 are accepted. In this state the CPU does not increment the IFF even if the CPU accepts an interrupt request of level 7. (3) Interrupt nesting (main) EI 3 [1] INTT0 (Level 3) [9] [8] IFF3 RETI IFF4 [2] [3] INTT1 (Level 4) [7] [6] IFF4 RETI IFF5 [4] (INTT0 interrupt routine) (4) Software interrupt (INTT1 interrupt routine) (main) DI [1] [2] (SWI3 routine) [5] SWI 3 [5] [4] [3] RETI During processing an interrupt of priority level 3, the IFF is set to 4. When an interrupt with a level higher than 4 is generated, the CPU accepts the interrupt with the higher priority level, causing interrupt processing to nest. The CPU accepts a software interrupt request during DI status (IFF = 7) because the request has a priority of level 7. The IFF is not changed by the software interrupt. (5) Timing of interrupt acceptance (main) EI 3 [1] INTT0 (Level 3) [8] [7] [6] RETI RETI INTT1 (Level 4) [2] (INTT0 interrupt routine) (INTT1 interrupt routine) [3] XXX [5] [4] (underline): Instruction [1], [2], ...: Execution flow If an interrupt with a priority level higher than the interrupt currently being processed is generated, the CPU accepts the interrupt with the higher level. The program counter which returns at [5] is the state address of the INTT0 interrupt routine. 93CS40-37 2004-02-10 TMP93CS40/TMP93CS41 The addresses 008000H to 0080FFH (256 bytes) of the TMP93CS40 and TMP93CS41 are assigned as interrupt vector areas. Table 3.4.1 TMP93CS40/TMP93CS41 Interrupt Table Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 - - Type Interrupt Source Reset, or SWI0 instruction SWI 1 instruction Illegal instruction, or SWI2 SWI 3 instruction SWI 4 instruction SWI 5 instruction SWI 6 instruction SWI 7 instruction NMI: NMI pin input INTWD: Watchdog timer INT0: INT0 pin input INT4: INT4 pin input INT5: INT5 pin input INT6: INT6 pin input INT7: INT7 pin input (Reserved) INTT0: 8-bit timer 0 INTT1: 8-bit timer 1 INTT2: 8-bit timer 2/PWM 0 INTT3: 8-bit timer 3/PWM 1 INTTR4: 16-bit timer 4 (TREG4) INTTR5: 16-bit timer 4 (TREG5) INTTR6: 16-bit timer 5 (TREG6) INTTR7: 16-bit timer 5 (TREG7) INTRX0: Serial receive (Channel 0) INTTX0: Serial send (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial send (Channel 1) INTAD: AD conversion completion (Reserved) (Reserved) Vector Value "v" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 to F 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 C H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Address Referring to Vector 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 to F 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 C H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Micro DMA Start Vector - - - - - - - - 08H 09H 0AH 0BH 0CH 0DH 0EH - 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH - to - Nonmaskable Maskable 93CS40-38 2004-02-10 TMP93CS40/TMP93CS41 Setting to reset and interrupt vectors 1. Reset vector 8000H 8001H 8002H 8003H PC<7:0> PC<15:8> PC<23:16> XX The vector base addresses are dependent on the products. Type No. Vector Base Address PC Setting Sequence after Reset Notes P27 to P20 and A23 to A16 pins are defined as input ports and are pulled down in resetting. The logic data item is 00H. When port 2 is used for the A23 to A16 pins to access the program ROM, set PC (23 to 16) to 00H and set the reset vector to lie within the area 0000H to FFFFH. (This is applicable mainly to products without ROM.) TMP93CS40/CS41 TMP93CM40 TMP93PS40 TMP93CW40/CW41 TMP93PW40 008000H PC (7:0) Data in location 8000H PC (15:8) Data in location 8001H PC (23:16) Data in location 8002H 2. Interrupt vector (except reset vector) +0 +1 +2 +3 PC<7:0> PC<15:8> PC<23:16> XX Address refers to vector XX: Don't care 93CS40-39 2004-02-10 TMP93CS40/TMP93CS41 Setting example: Set the reset vector to 8100H, NMI vector to 9ABCH and INTAD vector to 123456H. ORG DL ORG DL ORG DL ORG LD ORG LD ORG LD 8000H 008100H 8020H 009ABCH 8070H 123456H 8100H A, B 9ABCH B, C 123456H C, A ; Reset = 8100H ; NMI = 9ABCH ; INTAD = 123456H Note: ORG and DL are assembler directives. ORG: Control location counter DL: Defines long word (32-bit) data 93CS40-40 2004-02-10 TMP93CS40/TMP93CS41 3.4.2 Micro DMA In addition to the conventional interrupt processing, the TMP93CS40 and TMP93CS41 also have a micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether it is to be processed in micro DMA mode or in general-purpose interrupt mode. The CPU performs micro DMA processing only if that mode is requested. The micro DMA of the TMP93CS40 and TMP93CS41 can process at very high speed compared with the TLCS-90 micro DMA because it has transfer parameters in dedicated registers in the CPU. Since those dedicated registers are assigned as CPU control registers, they can only be accessed by the LDC instruction. (1) Micro DMA operation Micro DMA operation starts when the accepted interrupt vector value matches the micro DMA start vector value set in the interrupt controller. The micro DMA has four channels, so that it can be set for up to four types of interrupt sources at the same time. When a micro DMA interrupt is accepted, data are automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. If the value in the counter after decrementing is other than "0", micro DMA processing is completed; if the value in the counter after decrementing is "0", general-purpose interrupt processing is performed. In read-only mode, which provides for DRAM refresh, the value in the counter is ignored and a dummy read operation is repeated. 32-bit control registers are used for setting transfer source and destination addresses. However, the TMP93CS40 and TMP93CS41 have only 24 address pins for output. A 16-Mbyte space is available for the micro DMA. There are two data transfer modes: One-byte mode and one-word mode. Incrementing, decrementing, and fixing the transfer source and destination addresses after transfer can be done in both modes. Therefore data can easily be transferred between I/O and memory and between different I/Os. For details of transfer modes, see the description of transfer mode registers. The transfer counter has 16 bits, so up to 65536 transfers (The maximum when the initial value of the transfer counter is 0000H) can be performed for one interrupt source by micro DMA processing. When the transfer counter is decremented to "0" after data are transferred by micro DMA, general-purpose interrupt processing is performed. After processing general-purpose interrupt, restarting the interrupts of the same channel restarts transfer counter from 65536. It is necessary to reset the transfer counter in general-purpose interrupt processing routine. the the the the Interrupt sources handled by micro DMA processing are 20 in total, and the micro DMA start vectors are listed in Table 3.4.1. The following timing chart is a micro DMA cycle of the transfer address increment (INC) mode (The other modes are the same as this except for the read-only mode). (Conditions: MAX mode, 16-bit bus width for 16 Mbytes, 0 waits.) 93CS40-41 2004-02-10 1 state DM2 DM5 DM6 DM11 DM12 DM3 DM4 DM7 DM8 DM9 DM10 (Note 1) (Note 2) (Note 3) (Note 3) DM13 DM14 (Note 3) DM15 DM16 DM1 X1 ALE A0 to A15 D0 to D15 A0 to A15 AD0 to AD15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A16 to A23 Dummy Source address Destination address Dummy Dummy Address Address + 2 Address + 4 Figure 3.4.2 Micro DMA Cycle (Count 0) 93CS40-42 RD WR, HWR Note 1: These 2 states are added in the case that the bus width of the source address area is 8 bits. Note 2: These 2 states are added in the case that the bus width of the destination address area is 8 bits. Note 3: This may be a dummy cycle with an instruction queue buffer. TMP93CS40/TMP93CS41 2004-02-10 (Note 1) DM2 DM5 DM6 DM11 DM12 DM3 DM4 DM7 DM8 DM9 DM10 DM13 DM14 DM15 (Note 2) (Note 3) (Note 3) DM16 DM1 X1 ALE A0 to A15 D0 to D15 A0 to A15 AD0 to AD15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A16 to A23 Dummy Destination address Source address Dummy Address Dummy Address + 2 Dummy RD WR, HWR (Note 4) DM18 DM19 DM20 DM21 DM22 DM23 DM25 DM26 DM24 DM27 (Note 4) (Note 4) DM28 DM29 DM30 DM31 DM32 DM17 X1 ALE XSP - 6 XSP - 4 XSP - 2 Dummy 8000H + V 8002H + V Dummy AD0 to AD15 Dummy Figure 3.4.3 Micro DMA Cycle (Count = 0) DM34 DM35 DM36 DM37 Address Address + 2 93CS40-43 RD WR, HWR DM33 Note 1: These 2 states are added in the case that the bus width of the source address area is 8 bits or the address starts from an odd number. Note 2: These 2 states are added in the case that the bus width of the destination address area is 8 bits or the address starts from an odd number. Note 3: This may be a dummy cycle with an instruction queue buffer. Note 4: These 2 states are added in the case that the bus width of the stack address area is 8 bits or the stack pointer starts from an odd number. X1 ALE AD0 to AD15 Dummy RD WR, HWR TMP93CS40/TMP93CS41 2004-02-10 TMP93CS40/TMP93CS41 (2) Register configuration (CPU control registers) Channel0 DMAS0 DMAD0 DMAC0 DMAM0 Channel1 DMAS1 DMAD1 DMAC1 DMAM1 Channel2 DMAS2 DMAD2 DMAC2 DMAM2 Channel3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits Transfer source address register 3 Transfer destination address register 3 Transfer counter register 3 Transfer mode register 3 Transfer source address register 2 Transfer destination address register 2 Transfer counter register 2 Transfer mode register 2 Transfer source address register 1 Transfer destination address register 1 Transfer counter register 1 Transfer mode register 1 Transfer source address register 0 Transfer destination address register 0 Transfer counter register 0 Transfer mode register 0 (1 to 65536) (Use only lower 24 bits.) These control registers can only be set with the "LDC cr, r" instruction. Example: LD LDC LD LDC LD LDC LD LDC XWA, 100H DMAS0, XWA XWA, 50H DMAD0, XWA WA, 40H DMAC0, WA A, 05H DMAM0, A 93CS40-44 2004-02-10 TMP93CS40/TMP93CS41 (3) Transfer mode register details 0 0 0 0 Mode Note: When setting values for this register, set the upper 4 bits to 0. Execution time Z: 0 = byte transfer, 1 = word transfer 0 0 0 Z Transfer destination address INC mode .................................... for I/O to memory (DMADn+)(DMASn) DMACnDMACn - 1 if DMACn = 0 then INT. Transfer destination address DEC mode ................................... for I/O to memory (DMADn-)(DMASn) DMACnDMACn - 1 if DMACn = 0 then INT. Transfer source address INC mode........................................... for memory to I/O (DMADn)(DMASn+) DMACnDMACn - 1 if DMACn = 0 then INT. Transfer source address DEC mode ......................................... for memory to I/O (DMADn)(DMASn-) DMACnDMACn - 1 if DMACn = 0 then INT. Fixed address mode.................................................................. I/O to I/O (DMADn)(DMASn) DMACnDMACn - 1 if DMACn = 0 then INT. Read-only mode ........................................................................ for DRAM refresh Dummy(DMASn) ; Reads 4 bytes. DMASnDMASn + 4 ; Increments lower word only. DMACnDMACn - 1 Counter mode ........................................................................... for interrupt counter DMASnDMASn + 1 DMACnDMACn - 1 if DMACn = 0 then INT. 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 14 states (1.4 s) 11 states (1.1 s) 0 0 1 Z 0 1 0 Z 0 1 1 Z 1 0 0 Z 1 0 1 0 1 0 1 1 Note 1: n: corresponds to micro DMA channels 0 to 3. DMADn+/DMASn+: Post-increment (Increments register value after transfer.) DMADn-/DMASn-: Post-decrement (Decrements register value after transfer.) Note 2: Execution time: When setting source address/destination address area to 16-bit bus, 0 waits. Clock condition: fc = 20 MHz, clock gear: 1 (fc) Note 3: Do not use any codes for transfer mode registers other than those indicated above. 93CS40-45 2004-02-10 TMP93CS40/TMP93CS41 When the hardware configuration is as follows: DRAM mapping size: DRAM data bus size: = 1 Mbyte = 8 bits DRAM mapping address range: = 100000H to 1FFFFFH Set the following registers first; refresh is performed automatically. 1. Register initial value setting LD LDC LD LDC 2. 3. XIX, 100000H DMAS0, XIX A, 00001010B ... Read only mode (for DRAM refresh) DMAM0, A ... Mapping start address Timer setting Set the timers so that interrupts are generated at intervals of 62.5 s or less. Interrupt controller setting Set the timer interrupt mask higher than the mask for other interrupts. Write the above timer interrupt vector value into the micro DMA start vector register, DMA0V. (Operation description) The DRAM data bus is an 8-bit bus and the micro DMA is in read-only mode (4 bytes), so refresh is performed four times per interrupt. When a 512-refresh per 8 ms DRAM is connected, DRAM refresh is performed sufficiently if the micro DMA is started every 15.625 s x 4 = 62.5 s or less, since the timing is 15.625 s per refresh. (Overhead) Each processing time for read-only mode by the micro DMA is 1.8 s (18 states) at 20 MHz with an 8-bit data bus. In the above example, the micro DMA is started every 62.5 s, and 1.8 s / 62.5 s = 0.0288; thus, the overhead factor is 2.88%. Note: When the bus which must wait to accept the interrupt is released ( BUSAK = "0"), DRAM refresh is not performed because the micro DMA is generated by an interrupt. 93CS40-46 2004-02-10 TMP93CS40/TMP93CS41 3.4.3 Interrupt Controller Figure 3.4.4 is a block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the halt release signal circuit. Each interrupt channel (Total of 20 channels) in the interrupt controller has an interrupt request flag, interrupt priority setting register, and a register for storing the micro DMA start vector. The interrupt request flag is used to latch interrupt requests from peripheral devices. The flag is cleared to 0 when any of the following conditions are met. * * * Upon resetting When the CPU reads the interrupt vector after acceptance of an interrupt. When the CPU executes an instruction that clears the interrupt from that channel (Writes 0 in For example, to clear the INT0 interrupt request, after the DI instruction set the register INTE0AD as follows. INTE0AD - - - - 0 - - - Clears the INT0 flip-flop. The status of the interrupt request flag is detected by reading the corresponding clear bit. This also allows the interrupt to be identified by the software. The interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., INTE0AD or INTE45) provided for each interrupt source. Interrupt priority levels to be set range from or 1 to 6. Except for NMIs (Non-maskable interrupts), writing 0 or 7 as the interrupt priority disables the corresponding interrupt request. The priority of non-maskable interrupt sources ( NMI pin, watchdog timer, etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance with the default ranking of priorities. The interrupt controller selects the interrupt request with the highest priority among the simultaneous interrupts, and sends it and its vector address to the CPU. The CPU compares the priority value 93CS40-47 2004-02-10 Interrupt controller CPU 1 NMI Interrupt enable flag on CPU side RESET Interrupt request Priority encoder signal to CPU IFF2 to 0 3 3 INTRQ2 to 0 Interrupt vector read 3 1 7 Highest A priority B interrupt C level select Interrupt request flag S Q RESET R Interrupt vector V read V = 20H V = 24H Decoder A D Q CLR B C 6 6 INTWD Priority setting register Dn Dn + 1 Dn + 2 EI 1 to 7 DI Interrupt level detect Interrupt request signal Y1 Y2 Y3 Y4 Y5 Y6 INT0 Dn + 3 (Highest priority = 7) 20 RESET Interrupt request flag S Q R 1 2 3 4 5 6 7 D0 D1 D7 If INTRQ2 to 0 IFF2 to 0 then 1. Interrupt vector generation D2 D3 D4 D5 D6 During IDLE1 During STOP Figure 3.4.4 Block Diagram of Interrupt Controller 93CS40-48 5 4 D CLR 5 Match detect DMA0V DMA1V DMA2V DMA3V Q 5 4-input OR D4 D3 D2 D1 D0 Halt release RESET INT0 NMI INT4 INT5 INT6 INT7 INTT0 INTT1 INTT2 INTT3 INTTR4 INTTR5 INTTR6 INTTR7 INTRX0 INTTX0 INTRX1 INTTX1 INTAD Interrupt request flag read Interrupt request clear Dn + 3 Interrupt request V read V = 28H V = 2CH V = 30H V = 34H V = 38H V = 40H V = 44H V = 48H V = 4CH V = 50H V = 54H V = 58H V = 5CH V = 60H V = 64H V = 68H V = 6CH V = 70H Micro DMA start vector setting register Micro DMA request RESET A B Micro DMA channel priority encoder TMP93CS40/TMP93CS41 0 1 2 3 2 2 Micro DMA channel specification 2004-02-10 TMP93CS40/TMP93CS41 (1) Interrupt priority setting register Symbol Address 7 IADC R/W 0 I5C R/W 0 I7C R/W 0 IT1C R/W 0 IPW1C R/W 0 IT5C R/W 0 IT7C R/W 0 ITX0C R/W 0 ITX1C R/W 0 0 0 INTTX1 INTES1 0078H ITX1M2 ITX1M1 W 0 0 ITX1M0 IRX1C R/W 0 0 0 INTTX0 INTES0 0077H ITX0M2 ITX0M1 W 0 0 ITX0M0 IRX0C R/W 0 0 INTRX1 IRX1M2 IRX1M1 W 0 0 IRX1M0 0 IT7M2 0 IT5M2 0 IPW1M2 0 IT1M2 0 INT7 INTE67 0072H I7M2 I7M1 W 0 IT1M1 W 0 IPW1M1 W 0 IT5M1 W 0 IT7M1 W 0 0 0 IT7M0 INTTR7 (TREG7) INTET76 0076H IT6C R/W 0 0 INTRX0 IRX0M2 IRX0M1 W 0 0 IRX0M0 0 IT5M0 INTTR5 (TREG5) INTET54 0075H IT4C R/W 0 0 IT6M2 0 IPW1M0 INTT3 (Timer3/PWM1) INTEPW10 0074H IPW0C R/W 0 0 IT4M2 0 IT1M0 INTT1 (Timer1) INTET10 0073H IT0C R/W 0 0 IPW0M2 I7M0 I6C R/W 0 0 IT0M2 I6M2 0 INT5 INTE45 0071H I5M2 I5M1 W 0 0 I5M0 I4C R/W 0 0 INT6 I6M1 W 0 IT0M1 W 0 IPW0M1 W 0 IT4M1 W 0 IT6M1 W 0 0 0 IT6M0 INTTR6 (TREG6) 0 IT4M0 INTTR4 (TREG4) 0 IPW0M0 INTT2 (Timer2/PWM0) 0 IT0M0 INTT0 (Timer0) I6M0 I4M2 6 INTAD IADM2 5 IADM1 W 0 4 IADM0 0 3 I0C R/W 0 2 INT0 I0M2 0 INT4 1 I0M1 W 0 I4M1 W 0 0 Interrupt source INTE0AD 0070H I0M0 0 I4M0 0 Bit symbol Read/Write After reset IxxM2 0 0 0 0 1 1 1 1 IxxC 0 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Prohibits interrupt request. Sets interrupt request level to "1". Sets interrupt request level to "2". Sets interrupt request level to "3". Sets interrupt request level to "4". Sets interrupt request level to "5". Sets interrupt request level to "6". Prohibits interrupt request. Function (Write) Clears interrupt request flag. Don't care Function (Read) Indicates no interrupt request. Indicates interrupt request. Note 1: Read-modify-write is prohibited. Note 2: This note is about clearing interrupt request flags. The interrupt request flags of INTAD, INTRX0, and INTRX1 are not cleared by writing "0" to IxxC because they are level-sense interrupts. Figure 3.4.5 Interrupt Priority Setting Register 93CS40-49 2004-02-10 TMP93CS40/TMP93CS41 (2) External interrupt control Interrupt Input Mode Control Register 7 IIMC (007BH) Bit symbol Read/Write After reset Function 6 5 4 3 2 I0IE W 0 1: INT0 input enable 1 I0LE W 0 0: INT0 edgesense mode 1: INT0 levelsense mode 0 NMIREE W 0 1: Can be accepted in NMI rising edge. INT0 input enable (Note 1) 0 1 INT0 disable (P87 function only) Input enable NMI rising edge enable 0 1 Interrupt request generation at falling edge Interrupt request generation at rising and falling edge Note 1: The INT0 pin can also be used for standby release as described in section 3.3.4. Even if the pin is not used for standby release, setting this register to "0" maintains the port function during standby mode. Note 2: This is a case of changing from level-sence to edge-sence for INT0 pin mode. Execution example: LD (INTE0AD) ,xxxx0000B LD (IIMC) ,xxxxx10xB ; INT0 disable, clear the request flag. ; Change from level to edge. ; Set interrupt level "n" for INT0, clear the request flag. Note 3: Read-modify-write is prohibited. Note 4: IMC INT0 level enable (Note 2) 0 1 Rising edge detect interrupt High level interrupt LD (INTE0AD) ,xxxx0nnnB Figure 3.4.6 Interrupt Input Mode Control Register Table 3.4.2 Setting of External Interrupt Pin Function Interrupt NMI Pin Name - Mode Falling edge Falling and rising edges Rising edge Setting Method IIMC INT0 P87 High level Rising edge INT4 P80 Falling edge INT5 P81 Rising edge Rising edge T5MOD INT6 P84 Falling edge INT7 P85 Rising edge 93CS40-50 2004-02-10 TMP93CS40/TMP93CS41 (3) Micro DMA start vector When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the bits 2 to 6 of the interrupt vector with each channel's micro DMA start vector. When the two match, the interrupt from the channel whose value matched is processed in micro DMA mode. If the interrupt vector matches more than one channel, the channel with the lower channel number has a higher priority. Micro DMA 0 State Vector 7 DMA0V (007CH) Bit symbol Read/Write After reset Function 0 0 6 5 4 DMA0V4 3 DMA0V3 2 DMA0V2 W 0 1 DMA0V1 0 0 DMA0V0 0 Micro DMA channel 0 processed by matching bits 2 to 6 of the interrupt vector. Micro DMA 1 State Vector 7 DMA1V (007DH) Bit symbol Read/Write After reset Function 0 0 6 5 4 DMA1V4 3 DMA1V3 2 DMA1V2 W 0 1 DMA1V1 0 0 DMA1V0 0 Micro DMA channel 1 processed by matching bits 2 to 6 of the interrupt vector. Micro DMA 2 State Vector 7 DMA2V (007EH) Bit symbol Read/Write After reset Function 0 0 6 5 4 DMA2V4 3 DMA2V3 2 DMA2V2 W 0 1 DMA2V1 0 0 DMA2V0 0 Micro DMA channel 2 processed by matching bits 2 to 6 of the interrupt vector. Micro DMA 3 State Vector 7 DMA3V (007FH) Bit symbol Read/Write After reset Function 0 0 6 5 4 DMA3V4 3 DMA3V3 2 DMA3V2 W 0 1 DMA3V1 0 0 DMA3V0 0 Micro DMA channel 3 processed by matching bits 2 to 6 of the interrupt vector. Note: Read-modify-write is not possible for DMA0V to DMA3V. Figure 3.4.7 Micro DMA State Vector Register 93CS40-51 2004-02-10 TMP93CS40/TMP93CS41 (4) Notes The instruction execution unit and the bus interface unit of this CPU operate independently of each other. Therefore, if the instruction used to clear the interrupt request flag of an interrupt is fetched before the interrupt is generated, it is possible that the CPU might accept the interrupt and execute the fetched instruction to clear the interrupt request flag while reading the interrupt vector. If so, the CPU would start the interrupt processing from the address "8028H". To avoid the above occurring, clear the interrupt request flag by entering the instruction to clear the flag after the DI instruction. In the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing instruction and following more than one instruction are executed. When EI instruction is placed immediately after clearing instruction, an interrupt becomes enable before interrupt request flags are cleared. In the case of changing the value of the interrupt mask register 93CS40-52 2004-02-10 TMP93CS40/TMP93CS41 3.5 Functions of Ports The TMP93CS40 has 79 bits for I/O ports. The TMP93CS41 has 61 bits for I/O ports because port 0, port 1, P30, and P31 are dedicated pins for AD0 to AD7, AD8 to AD15 or A8 to A15, RD , and WR . These port pins have I/O functions for the built-in CPU and internal I/Os as well as general-purpose I/O port functions. Table 3.5.1 lists the function of each port pin. Table 3.5.2 lists I/O registers and their specifications. Table 3.5.1 Functions of Ports Port No. Port 0 Port 1 Port 2 Port 3 Pin No. P00 to P07 P10 to P17 P20 to P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P50 to P57 P60 to P67 P70 P71 P72 P73 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PA0 to PA6 PA7 Number of Pins 8 8 8 1 1 1 1 1 1 1 1 1 1 1 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 Direction I/O I/O I/O Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - - - - - Direction Setting Unit Bit Bit Bit (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Name for Built-in Function AD0 to AD7 AD8 to AD15/A8 to A15 A0 to A7/A16 to A23 RD WR HWR WAIT BUSRQ BUSAK R/ W RAS CS0 / CAS0 CS1 / CAS1 CS2 / CAS2 Port 4 Port 5 Port 6 Port 7 AN0 to AN7 PG00 to PG03, PG10 to PG13 TI0 TO1 TO2 TO3 TI4/INT4 TI5/INT5 TO4 TO5 TI6/INT6 TI7/INT7 TO6 INT0 TXD0 RXD0 CTS0 /SCLK0 Port 8 Port 9 TXD1 RXD1 SCLK1 XT1 XT2 SCOUT Port A R: = With programmable pull-up resistor = With programmable pull-down resistor. 93CS40-53 2004-02-10 TMP93CS40/TMP93CS41 Table 3.5.2 I/O Registers and Specifications (1/2) Port No. Port 0 Pin No. P00 to P07 Input port (Note 1) Output port (Note 1) AD0 to AD7 bus Function I/O Register Pn x x x x x x x 1 0 PnCR 0 1 PnFC None 0 0 1 1 0 0 0 1 1 0 1 1 0 1 0 0 0 1 None 1 1 1 1 1 0 0 0 0 0 0 1 1 1 None x 0 1 0 1 0 0 1 0 1 None Port 1 P10 to P17 Input port (Note 1) Output port (Note 1) AD8 to AD15 bus (Note 2) A8 to A15 output (Note 2) Port 2 P20 to P27 Input port (without PD) Input port (with PD) Output port A0 to A7 output (Note 1) A16 to A23 output x 1 1 Port 3 P30 Output port (Note 1) Outputs RD only when accessing external space Always outputs RD x 1 0 P31 P32 to P37 Output port (Note 1) Outputs WR only when accessing external space Input port (without PU) Input port (with PU) Output port x x 0 1 None 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 P32 P33 P34 P35 P36 P37 Port 4 P40 to P41 HWR output WAIT input (without PU) WAIT input (with PU) BUSRQ input (without PU) BUSRQ input (with PU) BUSAK output x x 0 1 0 1 R/ W output RAS output Input port (without PU) Input port (with PU) Output port x x x 0 1 x 1 0 P42 Input port (without PD) Input port (with PD) Output port CS0 output (Note 3) CS1 output (Note 3) CS2 output (Note 3) P40 P41 P42 Port 5 Port 6 P50 to P57 P60 to P67 Input port AN0 to AN7 input (Note 4) Input port (without PU) Input port (with PU) Output port PGn output x x x x x x 0 1 0 0 1 1 0 0 0 1 x x x: Don't care Note 1: In the case of the TMP93CS41F, this function is not available. Note 2: In the case of the TMP93CS41F, this function is fixed by AM8/ AM16 pin. Note 3: CS/WAIT control register BnCH 93CS40-54 2004-02-10 TMP93CS40/TMP93CS41 Table 3.5.3 I/O Registers and Specifications (2/2) Port No. Port 7 Pin No. P70 to P73 Function Input port (without PU) Input port (with PU) Output port I/O Register Pn 0 1 PnCR 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 PnFC 0 0 0 None 1 1 1 0 0 0 None None None None 1 1 1 None 0 0 0 1 1 None None 1 0 0 1 0 0 None x 0 1 P70 P71 P72 P73 Port 8 P80 to P87 TI0 input (without PU) TI0 input (with PU) TO1 output TO2 output TO3 output Input port (without PU) Input port (with PU) Output port x x x 0 1 x 0 1 0 1 0 1 0 1 P80 P81 P84 P85 P82 P83 P86 P87 (Note 5) Port 9 P90 to P95 TI4/INT4 input (without PU) TI4/INT4 input (with PU) TI5/INT5 input (without PU) TI5/INT5 input (with PU) TI6/INT6 input (without PU) TI6/INT6 input (with PU) TI7/INT7 input (without PU) TI7/INT7 input (with PU) TO4 output TO5 output TO6 output INT0 input (without PU) INT0 input (with PU) Input port (without PU) Input port (with PU) Output port x x x 0 1 0 1 P90 P93 P91 P94 P92 TXD0 output TXD1 output RXD0 input (without PU) RXD0 input (with PU) RXD1 input (without PU) RXD1 input (with PU) SCLK0 output CTS0/SCLK0 input (without PU) CTS0/SCLK0 input (with PU) x x x 0 1 0 1 x 0 1 P95 SCLK1 output SCLK1 input (without PU) SCLK1 input (with PU) x 0 1 P96 to P97 Input port Output port (Note 6) XT1/2 (Note 7) Port A PA0 to PA7 PA7 Input port Output port SCOUT output (Note 8) x x x x x x None x: Don't care Note 5: When the P87 pin is used as INT0, the IIMC register has to be set to enable interrupt. Note 6: When using P96 to P97 as output ports, output goes through the open-drain buffer. Note 7: When P96 to P97 are used as XT1 to XT2, the SYSCR0 93CS40-55 2004-02-10 TMP93CS40/TMP93CS41 Resetting makes the port pins listed below function as general-purpose I/O ports. I/O pins programmable for input or output are then set to function as input ports, except for P96/XT1 and P97/XT2. A program is needed to set port pins for built-in functions. Because the TMP93CS41 needs external ROMs, some ports are permanently assigned for memory interfacing. * P00 to P07 AD0 to AD7 * P30 RD * P10 to P17 AD8 to AD15 (or A8 to A15) * P31 WR * Note about the bus release and programmable pull-up/pull-down I/O ports. When the bus is released ( BUSAK = "0"), the output buffers of AD0 to AD15 and A0 to A23, as well as the control signals ( RD , WR , HWR , R / W , RAS , CS0 / CAS0 to CS2 / CAS2 ) are all set to OFF and they go into a high-impedance state. However, the states of the built-in programmable pull-up/pull-down resistors are retained when the bus is released. These programmable pull-up/pull-down resistors can be switched ON or OFF by programming when they are used as input ports. When they are used as output ports, they cannot be switched by programming. Table 3.5.4 shows the pin states when the bus is released ( BUSAK = "0") Table 3.5.4 Pin States (when the bus is released) Pin Name P00 to P07 (AD0 to AD7) P10 to P17 (AD8 to AD15/A8 to A15) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P37 ( RAS ) Pin States (when the bus is released) Used as a Port The state is not changed. (does not go to high-impedance (High-Z).) Used for a Function Goes to high-impedance (High-Z). Goes to high-impedance (High-Z). The output buffer is OFF. The programmable pull-up resistor is ON only in the case that the output latch is equal to "1". The output buffer is OFF. The programmable pull-up resistor is ON only in the case that the output latch is equal to "1". The output buffer is OFF. The programmable pull-down resistor is ON only in the case that the output latch is equal to "0". Goes to high-impedance (High-Z). The output buffer is OFF. The programmable pull-up resistor is ON irrespective of the output latch. The output buffer is OFF. The state of the programmable pull-up resistor is retained when the bus is released. The output buffer is OFF. The state of the programmable pull-down resistor is retained when the bus is released. The output buffer is OFF. The programmable pull-down resistor is ON only in the case that the output latch is equal to "0". P36 ( R/ W ) P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) P42 ( CS2 / CAS2 ) P20 to P27 (A16 to A23) The state is not changed. (does not go to high-impedance (High-Z).) 93CS40-56 2004-02-10 TMP93CS40/TMP93CS41 Figure 3.5.1 shows an example of an interface circuit using some of the pins described in Table 3.5.4, in a case when the bus releasing function is used. When the bus is released, neither internal memory nor internal I/O can be accessed. However, the internal I/O continues to operate, so the watchdog timer (WDT) also continues to run. Therefore, be careful about bus releasing time and setting of the detection time of the WDT. P35 ( BUSAK ) 3 to 5 k P42 ( CS2 ) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P36 ( R/ W ) P37 ( RAS ) P40 ( CS0 ) P41 ( CS1 ) System control bus P20 (A16) to P27 (A23) Address bus (A23 to A16) Figure 3.5.1 Example of an Interface Circuit using the Bus Releasing Function A circuit like the one shown above is needed to fix the signal level in the case when the bus is released. Resetting sets P30 ( RD ) and P31 ( WR ) to output; P40 ( CS0 ), P41 ( CS1 ), P32 ( HWR ), P36 ( R/ W ), P37 ( RAS ), and P35 ( BUSAK ) all to input with pull-up resistor; as well as P42 ( CS2 ) and P20 to P27 (A16 to A23) to input with pull-down resistor. A circuit like the one above is also needed to fix the signal level after resetting, because of the possibility of conflict between the external pull-up resistor and the internal pull-down resistor. The resistance of the external pull-up resistor must be 3 to 5 k, and the resistance of the internal pull-down resistor is about 50 to 150 k. Using a pull-down resistor is recommended for P20 to P27 (A16 to A23); however, if this is not possible, a switching circuit like the one used for P42 ( CS2 ) may be used. 93CS40-57 2004-02-10 TMP93CS40/TMP93CS41 3.5.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P0CR. Resetting resets all bits of P0CR to "0", and sets port 0 to input mode. In addition to functioning as a general-purpose I/O port, port 0 also functions as an address data bus (AD0 to AD7). To access external memory, port 0 functions as an address data bus (AD0 to AD7), and all bits of the control register P0CR are cleared to "0". In the TMP93CS41, which needs external ROMs, port 0 always functions as an address data bus (AD0 to AD7) regardless of the value set in control register P0CR. Reset Direction control (on bit basis) P0CR write Internal data bus Output latch Output buffer P0 write S Selector A P0 read B A B Port 0 P00 to P07 (AD0 to AD7) S Selector Figure 3.5.2 Port 0 93CS40-58 2004-02-10 TMP93CS40/TMP93CS41 3.5.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P1CR and function register P1FC. Resetting resets all bits of output latch P1, control register P1CR, and function register P1FC to 0, and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 also functions as an address data bus (AD8 to AD15) or an address bus (A8 to A15). In the TMP93CS41, which needs external ROMs, port 1 always functions either as an address data bus (AD8 to AD15) when AM8/ AM16 = "0", or as an address bus (A8 to A15) when AM8/ AM16 = "1", regardless of the value set in control register P1CR. Reset Direction control (on bit basis) P1CR write Function control (on bit basis) Internal data bus P1FC write Output latch Output buffer P1 write S Selector A P1 read B Port 1 P10 to P17 (AD8 to AD15/A8 to A15) Figure 3.5.3 Port 1 93CS40-59 2004-02-10 TMP93CS40/TMP93CS41 Port 0 Register 7 P0 (0000H) Bit symbol Read/Write After reset P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Input mode (Output latch register becomes undefined.) Port 0 Control Register 7 P0CR (0002H) Bit symbol Read/Write After reset Function 0 0 0 0 P07C 6 P06C 5 P05C 4 P04C R/W 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 0: Input 1: Output (when externally accessed, port 0 becomes AD7 to AD0 and P0CR is cleared to 0.) Port 0 I/O setting 0 1 Input Output Port 1 Register 7 P1 (0001H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Input mode (Output latch register is cleared to "0".) Port 1 Control Register 7 P1CR (0004H) Bit symbol Read/Write After reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C R/W 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 < Port 1 Function Register 7 P1FC (0005H) Bit symbol Read/Write After reset Function 0 0 0 0 P17F 6 P16F 5 P15F 4 P14F R/W 3 P13F 0 2 P12F 0 1 P11F 0 0 P10F 0 < Note 1: Read-modify-write is prohibited for registers P0CR, P1CR, and P1FC. Note 2: Port 1 function setting P1FC 0 1 Address data bus (AD15 to AD8) Address bus (A15 to A8) 0 1 Input port Output port Figure 3.5.4 Registers for Ports 0 and 1 93CS40-60 2004-02-10 TMP93CS40/TMP93CS41 3.5.3 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P2CR and function register P2FC. Resetting resets all bits of output latch P2, control register P2CR and function register P2FC to "0". It also sets port 2 to input mode and connects a pull-down resistor. In addition to functioning as a general-purpose I/O port, port 2 also functions as an address bus (A0 to A7) or (A16 to A23). To use port 2 as an address bus, write 1 to the output latches to turn off the programmable pull-down resistors. A16 to A23 B Selector A0 to A7 Reset A S Direction control (on bit basis) P2CR write Function control (on bit basis) Internal data bus P2FC write S B Selector Output latch P2 write A Output buffer N-ch Port 2 P20 to P27 (A0 to A7 or A16 to A23) S Selector B Programmable pull down A P2 read Figure 3.5.5 Port 2 93CS40-61 2004-02-10 TMP93CS40/TMP93CS41 Port 2 Register 7 P2 (0006H) Bit symbol Read/Write After reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Input mode (Output latch register is cleared to "0".) Port 2 Control Register 7 P2CR (0008H) Bit symbol Read/Write After reset Function 0 0 0 0 P27C 6 P26C 5 P25C 4 P24C W 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 < Port 2 Function Register 7 P2FC (0009H) Bit symbol Read/Write After reset Function 0 0 0 0 P27F 6 P26F 5 P25F 4 P24F W 3 P23F 0 2 P22F 0 1 P21F 0 0 P20F 0 < Note 1: Read-modify-write is prohibited for registers P2CR and P2FC. Note 2: When port P2 is used in the input mode, P2 register controls the built-in pull-down resistor. Read-modify-write is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up/pull-down resistors. Note 3: Port 2 function setting P2FC 0 1 Address data bus (A7 to A0) Address bus (A23 to A16) 0 1 Input port Output port Figure 3.5.6 Registers for Port 2 93CS40-62 2004-02-10 TMP93CS40/TMP93CS41 3.5.4 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR and function register P3FC. Resetting sets all bits of output latch P3 to P1, and control register P3CR (bits 0 and 1 are unused) and function register P3FC to 0. Resetting also outputs 1 from P30 and P31, sets P32 to P37 to input mode, and connects a pull-up resistor. In addition to functioning as a general-purpose I/O port, port 3 also functions as an I/O for the CPU's control/status signal. When the P30 pin is defined as RD signal output mode ( 93CS40-63 2004-02-10 TMP93CS40/TMP93CS41 Reset For TMP93CS41 Function control (on bit basis) P3FC write Internal data bus S Output latch P3 write A S Output buffer Selector P30 ( RD ) P31 ( WR ) B RD , WR P3 read Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P-ch P3FC write Programmable pull-up resistor Internal data bus S Output latch P3 write A S Output buffer Selector P32 ( HWR ) P35 ( BUSAK ) P36 ( R/ W ) P37 ( RAS ) B HWR , BUSAK , R/ W , RAS S Selector B A P3 read Figure 3.5.7 Port 3 (P30, P31, P32, P35, P36, P37) 93CS40-64 2004-02-10 TMP93CS40/TMP93CS41 Reset Direction control (on bit basis) P3CR write S Output latch P3 write S Selector A Internal WAIT B P-ch Programmable pull-up resistor P33 ( WAIT ) Output buffer Internal data bus P3 read Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P-ch P3FC write Programmable pull-up resistor Internal data bus S Output latch P3 write P34 ( BUSRQ ) S Selector B A P3 read Internal BUSRQ Figure 3.5.8 Port 3 (P33, P34) 93CS40-65 2004-02-10 TMP93CS40/TMP93CS41 Port 3 Register 7 P3 (0007H) Bit symbol Read/Write After reset Function 1 1 1 1 Input mode (Pull up) P37 6 P36 5 P35 4 P34 R/W 3 P33 1 2 P32 1 1 P31 1 0 P30 1 Output mode Port 3 Control Register 7 P3CR (000AH) Bit symbol Read/Write After reset Function 0 0 0: Input 0 P37C 6 P36C 5 P35C W 4 P34C 0 1: Output 3 P33C 0 2 P32C 0 1 0 I/O setting 0 Input 1 Output Port 3 Function Register 7 P3FC (000BH) Bit symbol Read/Write After reset Function 0 0: Port 1: RAS 0 0: Port 1: R/ W P37F 6 P36F W 5 P35F 0 0: Port 1: BUSAK 4 P34F 0 0: Port 1: BUSRQ 3 2 P32F 0 0: Port 1: HWR 1 P31F W 0 0: Port 1: WR 0 P30F 0 0: Port 1: RD Note 1: Read-modify-write is prohibited for registers P3CR and P3FC. Note 2: When port P3 is used in the input mode, the P3 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up/pull-down resistors. Note 3: When the P33/WAIT pin is used as a WAIT pin, set P3CR P30 ( RD ) function setting BUSRQ setting 0 1 P3FC BUSAK setting 1 0 0 "0" output Always RD output (for pseudo SRAM) "1" output RD output 1 1 1 only for external access P3FC RAS setting P31 ( WR ) function setting 0 "0" output 1 "1" output 1 1 0 1 WR output only for external access P3FC 1 1 HWR setting P3FC 1 P3CR Figure 3.5.9 Registers for Port 3 93CS40-66 2004-02-10 TMP93CS40/TMP93CS41 3.5.5 Port 4 (P40 to P42) Port 4 is a 3-bit general-purpose I/O port. I/O can be set on a bit basis using control register P4CR and function register P4FC. Resetting does the following: - Sets the P40 and P41 output latch registers to 1. - Resets all bits of the P42 output latch register, the control register P4CR, and the function register P4FC to 0. - Sets P40 and P41 to input mode and connects a pull-up resistor. - Sets P42 to input mode and connects a pull-down resistor. In addition to functioning as a general-purpose I/O port, port 4 also functions as a chip select output signal ( CS0 to CS2 or CAS0 to CAS2 ). 93CS40-67 2004-02-10 TMP93CS40/TMP93CS41 Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P-ch P4FC write Programmable pull-up resistor Internal data bus S Output latch P4 write A S Selector Output buffer P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) B CS0 / CAS0 , CS1 / CAS1 S Selector B A P4 read Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write Internal data bus R Output latch P4 write A S Output buffer Selector N-ch P42 ( CS2 / CAS2 ) B CS2 / CAS2 Programmable pull-down resistor S Selector B A P4 read Figure 3.5.10 Port 4 93CS40-68 2004-02-10 TMP93CS40/TMP93CS41 Port 4 Register 7 P4 (000CH) Bit symbol Read/Write After reset Function 0 (Pull down) 6 5 4 3 2 P42 1 P41 R/W Input mode 1 (Pull up) 0 P40 1 (Pull up) Port 4 Control Register 7 P4CR (000EH) Bit symbol Read/Write After reset Function 0 0: Input 6 5 4 3 2 P42C 1 P41C W 0 1: Output 0 P40C 0 I/O setting 0 1 Input Output Port 4 Function Register 7 P4FC (0010H) Bit symbol Read/Write After reset Function 0 0: Port 6 5 4 3 2 P42F 1 P41F W 0 P40F 0 0 1: CS / CAS Note 1: Read-modify-write is prohibited for registers P4CR and P4FC. Note 2: When port P4 is used in the input mode, the P4 register controls the built-in pull-up/pull-down resistor. Read-modify-write is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up/pull-down resistors. Note 3: To output chip select signal ( CS0 / CAS0 to CS2 / CAS2 ), set the corresponding bits of the control register P4CR and the function register P4FC to "1". Chip select/wait controller (B0CS, B1CS, B2CS) registers select the function of CS / CAS . Note 4: P4 0 1 0 1 0 1 Port (P40) CS0 / CAS0 Port (P41) CS1 / CAS1 Port (P42) CS2 / CAS2 Figure 3.5.11 Registers for Port 4 93CS40-69 2004-02-10 TMP93CS40/TMP93CS41 3.5.6 Port 5 (P50 to P57) Port 5 is an 8-bit input port, also used as an analog input pin for the internal AD converter. Internal data bus Port 5 P50 to P57 Port 5 read (AN0 to AN7) Conversion result register AD read AD converter Channel selector Figure 3.5.12 Port 5 Port 5 Register 7 P5 (000DH) Bit symbol Read/Write After reset P57 6 P56 5 P55 4 P54 R 3 P53 2 P52 1 P51 0 P50 Input mode Note: The input channel selection of the AD converter is set by AD converter mode register ADMOD2. Figure 3.5.13 Registers for Port 5 93CS40-70 2004-02-10 TMP93CS40/TMP93CS41 3.5.7 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port 6 as an input port and connects a pull-up resistor. It also sets all bits of the output latch to 1. In addition to functioning as a general-purpose I/O port, port 6 also functions as a pattern generator of PG0 or PG1 output. PG0 is assigned to P60 to P63; PG1, to P64 to P67. Writing 1 in the appropriate bit of the port 6 function register (P6FC) enables PG output. Resetting resets the function register P6CR, P6FC value to "0", and sets all bits to input ports. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write Internal data bus S Output latch P6 write PG0, 1 A S Selector P-ch Programmable pull up Port 6 P60 to P67 (PG00 to PG13) B S Selector B A P6 read Figure 3.5.14 Port 6 93CS40-71 2004-02-10 TMP93CS40/TMP93CS41 Port 6 Register 7 P6 (0012H) Bit symbol Read/Write After reset Function 1 1 1 1 P67 6 P66 5 P65 4 P64 R/W 3 P63 1 2 P62 1 1 P61 1 0 P60 1 Input mode (Pull up) Port 6 Control Register 7 P6CR (0014H) Bit symbol Read/Write After reset Function 0 0 0 0 0: Input P67C 6 P66C 5 P65C 4 P64C W 3 P63C 0 1: Output 2 P62C 0 1 P61C 0 0 P60C 0 Port 6 I/O setting 0 1 Input Output Port 6 Function Register 7 P6FC (0016H) Bit symbol Read/Write After reset Function 0 0 0: Port 0 1: PG1-OUT 0 P67F 6 P66F 5 P65F 4 P64F W 3 P63F 0 2 P62F 0 0: Port 1 P61F 0 1: PG0-OUT 0 P60F 0 Port 6 function setting 0 Note 1: Read-modify-write is prohibited for registers P6CR and P6FC. Note 2: When port P6 is used in the input mode, the P6 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up/pull-down resistors. 1 General-purpose port Stepping motor control/pattern generation port Figure 3.5.15 Registers for Port 6 93CS40-72 2004-02-10 TMP93CS40/TMP93CS41 3.5.8 Port 7 (P70 to P73) Port 7 is a 4-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port 7 as an input port and connects a pull-up resistor. In addition to functioning as a general-purpose I/O port, port 70 also functions as an input clock pin TI0; port 71 as an 8-bit timer output (TO1), port 72 as a PWM0 output (TO2), and port 73 as a PWM1 output (TO3) pin. Writing 1 in the corresponding bit of the port 7 function register (P7FC) enables output of the timer. Resetting resets the function register P7CR, P7FC value to 0, and sets all bits to input ports. Reset Direction control (on bit basis) P7CR write S Output latch P-ch Programmable pull up P70 (TI0) P7 write S B Selector P7 read TI0 Reset A Internal data bus Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write S Output latch P7 write Timer F/F out TO1: Timer 1 TO2: Timer 2 TO3: Timer 3 B Selector A B A S Selector P-ch Programmable pull up P71 to P73 (TO1 to TO3) P7 read S Figure 3.5.16 Port 7 93CS40-73 2004-02-10 TMP93CS40/TMP93CS41 Port 7 Register 7 P7 (0013H) Bit symbol Read/Write After reset Function 1 1 6 5 4 3 P73 2 P72 R/W 1 P71 1 0 P70 1 Input mode (Pull up) Port 7 Control Register 7 P7CR (0015H) Bit symbol Read/Write After reset Function 0 0 0: Input 6 5 4 3 P73C 2 P72C W 1 P71C 0 1: Output 0 P70C 0 Port 7 I/O setting 0 1 Input Output Port 7 Function Register 7 P7FC (0017H) Bit symbol Read/Write After reset Function 0 0: Port 1: TO3 6 5 4 3 P73F 2 P72F W 0 0: Port 1: TO2 1 P71F 0 0: Port 1: TO1 0 Setting P71 as TO1 P7FC Figure 3.5.17 Registers for Port 7 93CS40-74 2004-02-10 TMP93CS40/TMP93CS41 3.5.9 Port 8 (P80 to P87) Port 8 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port 8 as an input port and connects a pull-up resistor. It also sets all bits of the output latch register P8 to 1. In addition to functioning as a general-purpose I/O port, port 8 also functions as an input for 16-bit timer 4 and 5 clocks, an output for 16-bit timer F/F 4, 5, and 6 output, and an input for INT0. Writing "1" in the corresponding bit of the port 8 function register (P8FC) enables those functions. Resetting resets the function register P8CR, P8FC value to "0" and sets all bits to input ports. (1) P80 to P86 Reset Direction control (on bit basis) P8CR write S Output latch P8 write S B Selector P8 read TI4, TI5 TI6, TI7 A P-ch Programmable pull up P80 (TI4/INT4) P81 (TI5/INT5) P84 (TI6/INT6) P85 (TI7/INT7) Reset Internal data bus Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch P8 write Timer F/F out TO4: Timer 4 TO5: Timer 4 TO6: Timer 5 B Selector A B Programmable pull up P-ch A S Selector P82 (TO4) P83 (TO5) P86 (TO6) P8 read S Figure 3.5.18 Port 8 (P80 to P86) 93CS40-75 2004-02-10 TMP93CS40/TMP93CS41 (2) P87 (INT0) Port 87 is a general-purpose I/O port, and is also used as an INT0 pin for external interrupt request input. Reset Direction control (on bit basis) P8CR write S Output latch P8 write S B Selector P8 read A P-ch Programmable pull-up resistor P87 (INT0) Internal data bus INT0 interrupt Level/edge detect IIMC IIMC Figure 3.5.19 Port 87 93CS40-76 2004-02-10 TMP93CS40/TMP93CS41 Port 8 Register 7 P8 (0018H) Bit symbol Read/Write After reset Function 1 1 1 1 P87 6 P86 5 P85 4 P84 R/W 3 P83 1 2 P82 1 1 P81 1 0 P80 1 Input mode Port 8 Control Register 7 P8CR (001AH) Bit symbol Read/Write After reset Function 0 0 0 0: Input 0 P87C 6 P86C 5 P85C 4 P84C W 3 P83C 0 1: Output 2 P82C 0 1 P81C 0 0 P80C 0 Port 8 I/O setting 0 1 Input Output Port 8 Function Register 7 P8FC (001CH) Bit symbol Read/Write After reset Function 6 P86F W 0 0: Port 1: TO6 5 4 3 P83F W 0 0: Port 1: TO5 2 P82F W 0 0: Port 1: TO4 1 0 Setting P82 as TO4 Note 1: Read-modify-write is prohibited for registers P8CR and P8FC. Note 2: When port P8 is used in the input mode, the P8 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up/pull-down resistors. Note 3: The P80/TI4, P81/TI5, P84/TI6, and P85/TI7 pins do not have a register changing them from port to function. For example, when they are used as an input port, the incoming signal is input to the 16-bit timer as timer input. When P87/INT0 pin is used as an INT0 pin, set P8CR Setting P83 as TO5 P8FC Setting P86 as TO6 P8FC Figure 3.5.20 Registers for Port 8 93CS40-77 2004-02-10 TMP93CS40/TMP93CS41 3.5.10 Port 9 (P90 to P97) * Ports 90 to 95 Ports 90 to 95 constitute a 6-bit general-purpose I/O ports. I/Os can be set on a bit basis. Resetting sets P90 to P95 to an input port and connects a pull-up resistor. It also sets all bits of the output latch register to 1. In addition to functioning as a general-purpose I/O port, P90 to P95 can also function as an I/O for serial channels 0 and 1. Writing "1" in the corresponding bit of the port 9 function register (P9FC) enables those functions. Resetting resets the function register P9CR, P9FC value to "0" and sets all bits to input ports. * Ports 96 to 97 Ports 96 to 97 form a 2-bit general-purpose I/O port. I/Os can be set on a bit basis. The output buffer for P96 to P97 is an open-drain type buffer. Resetting sets the output latch and control registers to "1" and outputs high-impedance (High-Z). In addition to functioning as a general-purpose I/O port, P96 to P97 can also function as a low-frequency oscillator connecting pin for dual clock mode. The dual clock function can be set by programming system clock control register SYSCR0 and 1. (1) Ports 90, 93 (TXD0/TXD1) Ports 90 and 93 also function as serial channel TXD output pins in addition to I/O ports. They have a programmable open-drain function. 93CS40-78 2004-02-10 TMP93CS40/TMP93CS41 Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write Internal data bus S Output latch P9 write TXD0, TXD1 A S Selector P-ch Programmable pull-up resistor P90 (TXD0) Open-drain possible ODE B S Selector B A P9 read Figure 3.5.21 Ports 90 and 93 (2) Port 91, 94 (RXD0, RXD1) Ports 91 and 94 are I/O ports, and are also used as RXD input pins for serial channels. Reset Direction control (on bit basis) P9CR write P-ch Programmable pull-up resistor P91 (RXD0) P94 (RXD1) Internal data bus S Output latch P9 write S B Selector P9 read RXD0, RXD1 A Figure 3.5.22 Ports 91 and 94 93CS40-79 2004-02-10 TMP93CS40/TMP93CS41 (3) Port 92 ( CTS0 /SCLK0) Port 92 is an I/O port, and is also used as a CTS0 input pin and as a SCLK0 I/O pin for serial channels. Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write Internal data bus S Output latch A P9 write Selector SCLK0 B S P-ch Programmable pull-up resistor P92 (SCLK0/ CTS0 ) S Selector P9 read CTS0 B A SCLK0 Figure 3.5.23 Port 92 93CS40-80 2004-02-10 TMP93CS40/TMP93CS41 (4) Port 95 (SCLK1) Port 95 is a general-purpose I/O port. It is also used as a SCLK1 I/O pin for serial channel 1. Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write Internal data bus S Output latch A P9 write Selector SCLK1 B S P-ch Programmable pull-up resistor P95 (SCLK1) S Selector P9 read SCLK1 B A Figure 3.5.24 Port 95 93CS40-81 2004-02-10 TMP93CS40/TMP93CS41 (5) Port 96 (XT1), 97 (XT2) Ports 96 and 97 are general purpose I/O ports. They are also used as low-frequency oscillator connecting pins. Reset Bus 6 S Direction control (on bit basis) P9CR write Bus 6 S Output latch P9 write S Bus 6 Selector B Low-frequency oscillation enable P96 (XT1) Output buffer (Open-drain output) Internal data bus P9 read A (ON at "1") Bus 7 S Direction control (on bit basis) P9CR write Bus 7 S Output latch P9 write S P97 (XT2) Output buffer (Open-drain output) Low-frequency clock (fs) B Bus 7 Selector P9 read A Figure 3.5.25 Ports 96 and 97 93CS40-82 2004-02-10 TMP93CS40/TMP93CS41 Port 9 Register 7 P9 (0019H) Bit symbol Read/Write After reset Function Output mode 1 1 1 1 1 P97 6 P96 5 P95 4 P94 R/W 3 P93 2 P92 1 P91 0 P90 Input mode 1 1 1 Port 9 Control Register 7 P9CR (001BH) Bit symbol Read/Write After reset Function 1 1 0 0: Input 0 P97C 6 P96C 5 P95C 4 P94C W 3 P93C 0 1: Output 2 P92C 0 1 P91C 0 0 P90C 0 Port 9 I/O setting Note: Port 96 and 97's output buffer is an open-drain output type. 0 1 Input Output Port 9 Function Register 7 P9FC (001DH) Bit symbol Read/Write After reset Function 6 5 P95F W 0 0: Port 1: SCLK1 4 3 P93F W 0 0: Port 1: TXD1 2 P92F W 0 0: Port 1: SCLK0 1 0 P90F W 0 0: Port 1: TXD0 P90 TXD0 output setting (Note 3) Note 1: Read-modify-write is prohibited for registers P9CR and P9FC. Note 2: When port P9 is used in the input mode, the P9 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up/pull-down resistors. Note 3: When the TXD pin is set to be an open-drain output type, set 1 to bit0 (for TXD0 pin) or bit1 (for TXD1 pin) of the ODE register. The P91/RXD0 and P94/RXD1 pins do not have a register changing them from port to function. For example, when they are used as an input port, the incoming signal is input to the SIO as serial receiving data. P9FC P92 SCLK0 output setting P9FC P93 TXD1 output setting (Note 3) P9FC P95 SCLK1 output setting P9FC Note 4: Notes on using low-frequency oscillation circuit. To connect a low-frequency resonator to ports 96 and 97, it is necessary to set the following procedures to reduce the consumption of power. (Connecting to a resonator) Set P9CR Figure 3.5.26 Registers for Port 9 93CS40-83 2004-02-10 TMP93CS40/TMP93CS41 3.5.11 Port A (PA0 to PA7) Port A is an 8-bit general-purpose I/O port. I/Os can be set on a bit basis by control register PACR. Resetting sets port A to an input port by resetting PACR. It also sets all bits of the output latch register to "1". In addition to functioning as a general-purpose I/O port (Only PA7), PA7 can also function as an internal clock output pin. The output clock is fFPH or fSYS that is selected as oscillator output clock. It is selected by CKOCR Reset R Direction control (on bit basis) PACR write S Output latch PA write S Selector PA read A B Internal data bus PA0 to PA6 Figure 3.5.27 Port A0 to A6 93CS40-84 2004-02-10 TMP93CS40/TMP93CS41 Reset BUS 7 R Direction control (on bit basis) PACR write BUS 2 R Function control (on bit basis) CKOCR write Internal data bus BUS 7 S Output latch PA write A S Selector PA7 (SCOUT) B S Selector B BUS 7 A PA read fFPH A Selector fSYS B S CKOCR Figure 3.5.28 Port A7 93CS40-85 2004-02-10 TMP93CS40/TMP93CS41 Port A Register 7 PA (001EH) Bit symbol Read/Write After reset Function 1 1 1 1 Input mode PA7 6 PA6 5 PA5 4 PA4 R/W 3 PA3 1 2 PA2 1 1 PA1 1 0 PA0 1 Port A Control Register 7 PACR (001FH) Bit symbol Read/Write After reset Function 0 0 0 0 0: Input PA7C 6 PA6C 5 PA5C 4 PA4C W 3 PA3C 0 1: Output 2 PA2C 0 1 PA1C 0 0 PA0C 0 Clock Output Control Register 7 CKOCR (006DH) Bit symbol Read/Write After reset Function 0 0 6 5 4 3 SCOSEL 2 SCOEN R/W 1 ALEEN 0/1 0 CLKEN 0/1 Clock select Clock enable ALE enable CLK enable Note 1: Read-modify-write is prohibited for registers PACR. Note 2: The value after reset of CLK pin output control (Note 1) 0 1 High impedance CLK output ALE pin output control (Note 1) 0 1 High impedance ALE output SCOUT/PA7 pin control PACR 0 1 0 1 0 1 Input Port Output mode fFPH clock output (Note 3) fSYS clock output (Note 3) 1 Figure 3.5.29 Registers for Port A 93CS40-86 2004-02-10 TMP93CS40/TMP93CS41 3.6 Chip Select/Wait Controller, AM8/ AM16 pin The TMP93CS40 and TMP93CS41 have a built-in chip select/wait controller used to control chip select ( CS0 to CS2 pins), wait ( WAIT pin), and data bus size (8 or 16 bits) for any of the three block address areas. In addition, the AM8/ AM16 pin selects external data bus width. 3.6.1 AM8/ AM16 pin (1) Usage in the TMP93CS40 Set this pin to "1". After resetting, the CPU accesses the internal ROM with 16-bit bus width. The bus width when the CPU accesses an external area is set by the chip select/wait control register (described in section 3.6.3), P1CR and P1FC. (If this pin is set to 1, that value will be ignored and the value set by register will be active.) (2) Usage in the TMP93CS41 (2-1) When 16-bit bus width and 8-bit bus width are both used, or when 16-bit bus width only is used: Set this pin to "0". Then the AD8 to AD15 or A8 to A15 pins of port 1 are fixed to their A8 to A15 function compulsorily, and the values of P1CR and P1FC are ignored. The bus width when the CPU accesses an external area is set by the chip select/wait control register described in section 3.6.2. After a reset, 16-bit external program memory must be accessed before any other memory is accessed. (2-2) When 8-bit bus width only is used: Set this pin to "1". Then the AD8 to AD15 or A8 to A15 pins of port 1 are fixed to their A8 to A15 function compulsorily, and the values of P1CR and P1FC are ignored. The values of bit4 in 93CS40-87 20004-02-10 TMP93CS40/TMP93CS41 3.6.2 Address/Data Bus Pins Port 0, port 1 and port 2 function as an address and data bus for connecting the microcontroller to the external memories and I/O peripherals. 1. Products Number of Address Bus Pins Number of Data Bus Pins Number of Multiplexed Pins Mode Pins EA 2. TMP93CS41F (Note 4) 3. 4. TMP93CS40F (Note 2), (Note 3) max16 (to 64 Kbytes) 8 0 VIH VIL VIH AD0 to AD7 A8 to A15 A0 to A7 A15 to A0 AD7 to AD0 ALE A15 to A0 (Note 1) A7 D7 to A0 to D0 max24 (to 16 Mbytes) 8 8 VIL VIH AD0 to AD7 A8 to A15 A16 to A23 A23 to A8 AD7 to AD0 ALE A23 to A8 A7 to A0 D7 to D0 max24 (to 16 Mbytes) 16 16 max8 (to 256 Kbytes) 16 0 AM8/ AM16 Port 0 AD0 to AD7 AD8 to AD15 A16 to A23 A23 to A16 AD15 to AD0 ALE A23 to A16 A15 to A0 D15 to D0 AD0 to AD7 AD8 to AD15 A0 to A7 A7 to A0 AD15 to AD0 ALE A7 to A0 (Note 1) A15 D15 to A0 to D0 Port Function Port 1 Port 2 Timing Chart RD RD RD RD Note 1: In the cases of 3. and 4., the data bus signals output the addresses because the signals are also used as the address bus. By writing "0" to bit CKOCR 93CS40-88 20004-02-10 TMP93CS40/TMP93CS41 3.6.3 Control Registers Table 3.6.1 shows control registers. One block of the address areas is controlled by each of the 1-byte CS/WAIT control registers B0CS, B1CS, and B2CS. (1) Master enable bits Bit7 of the control registers (B0E, B1E, and B2E) are master bits used to specify setting enable (1) or disable (0). Resetting sets B0E and B1E to disable (0) and B2E to enable (1). (2) CS/CAS waveform select Bit5 of the control registers (B0CAS, B1CAS, and B2CAS) are used to specify the waveform mode output from the chip select pin (from CS0 to CS2 , or from CAS0 to CAS2 ). Setting these bits to 0 specifies CS0 to CS2 waveforms; setting them to 1 specifies CAS0 to CAS2 waveforms. Resetting clears bits 5 to 0. (3) Data bus size select Bit4 (B0BUS, B1BUS, and B2BUS) of the control register is used to specify data bus size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to 1 accesses the memory in 8-bit data bus mode. Changing data bus size depending on the access address is called dynamic bus sizing. Table 3.6.2 shows the details of the bus operation. This bit is changed by changing the state of the AM8/ AM16 pin. (4) Wait control Control register bits 3 and 2 93CS40-89 20004-02-10 TMP93CS40/TMP93CS41 (5) Address area specification Control register bits 1 and 0 Code Name Address 7 B0E Block0 CS/WAIT control register W 0 0068H 1: Master bit of bit0 to 6 6 5 B0CAS W 0 0: CS0 1: CAS0 4 B0BUS W 0 0: 16-bit bus 1: 8-bit bus B1BUS W 0 0: 16-bit bus 1: 8-bit bus B2BUS W 0 0: 16-bit bus 1: 8-bit bus 3 B0W1 W 0 2 B0W0 W 0 1 B0C1 W 0 0 B0C0 W 0 B0CS 00: 2 waits 01: 1 wait 10: (1 + n) waits 11: 0 waits B1W1 W 0 B1W0 W 0 00: 7F00H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B1C1 W 0 B1C0 W 0 B1E Block1 CS/WAIT control register W 0 0069H 1: Master bit of bit0 to 6 B1CAS W 0 0: CS1 1: CAS1 B1CS 00: 2 waits 01: 1 wait 10: (1 + n) waits 11: 0 waits B2W1 W 0 B2W0 W 0 00: 880H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B2C1 W 0 00: 8000H to 01: 400000H to 10: 800000H to 11: C00000H to B2C0 W 0 B2E Block2 CS/WAIT control register W 1 006AH 1: Master bit of bit0 to 6 B2CAS W 0 0: CS2 1: CAS2 B2CS 00: 2 waits 01: 1 wait 10: (1 + n) waits 11: 0 waits Note: Read-modify-write is prohibited for B0CS, B1CS, and B2CS. 93CS40-90 20004-02-10 TMP93CS40/TMP93CS41 Table 3.6.2 Dynamic Bus Sizing Operand Data Operand Start Memory Data CPU Address Size Address Size 8 bits 2n + 0 (Even number) 2n + 1 (Odd number) 16 bits 2n + 0 (Even number) 16 bits 2n + 1 (Odd number) 16 bits 32 bits 2n + 0 (Even number) 8 bits 8 bits 8 bits 16 bits 8 bits 16 bits 8 bits 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 2n + 1 2n + 2 2n + 4 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 bits 2n + 1 (Odd number) 8 bits 16 bits xxxxx: During a read, data input to the bus is ignored. While writing, the bus is at high impedance and the write strobe signal remains in active. 93CS40-91 20004-02-10 TMP93CS40/TMP93CS41 3.6.4 Chip Select Addresses Image An image of the actual addresses which can be specified by chip select is shown below. Out of the whole memory area, address areas that can be specified are divided into four parts. Addresses from 000000H to 3FFFFFH are further divided as follows: 7F00H to 7FFFH is specified for CS0; 880H to 7FFFH, for CS1; and 8000H to 3FFFFFH, for CS2. The reason is that a device other than ROM (e.g., RAM or I/O) might be connected externally. 7F00 to 7FFFH (256 bytes) designated as CS0 are mapped mainly for possible expansions to external I/O. 880H to 7FFFH (approx. 31 Kbytes) designated as CS1 are mapped mainly for possible extensions to external RAM. 8000H to 3FFFFFH (approx. 4 Mbytes) designated as CS2 are mapped mainly for possible extensions to external ROM. After resetting, CS2 is enabled in a 16-bit bus and 2-wait configuration. In the case of the TMP93CS41, which does not have a built-in ROM, the program is externally read at address 8000H with these settings (16-bit bus, 2 waits). With the TMP93CS40, which does have a built-in ROM, addresses from 8000H to 17FFFH are used as the internal ROM area; CS2 is disabled in this area. After resetting, the CPU reads the program from the built-in ROM in 16-bit bus, 0-wait mode. CS0 CS1 CS2 000000H 7F00H 8000H 400000H B0C1, 0 = "01" 800000H B0C1, 0 = "10" C00000H B0C1, 0 = "11" FFFFFFH (Mainly for I/O) (Mainly for RAM) (Mainly for ROM) B1C1, 0 = "11" B2C1, 0 = "11" B1C1, 0 = "10" B2C1, 0 = "10" B1C1, 0 = "01" B2C1, 0 = "01" B0C1, 0 = "00" B1C1, 0 = "00" B2C1, 0 = "00" Note 1: Note 2: Access priority is highest for built-in I/O, then built-in memory, and lowest for the chip select/wait controller. External areas other than CS0 to CS2 are accessed in 0 wait mode. For the TMP93CS40, the data bus width is fixed at 16 bits. For the TMP93CS41, the data bus width is 16 bits when AM8/ AM16 = 0, and 8 bits when AM8/ AM16 = 1. When using the chip select/wait controller, do not specify the same address area more than once. (However, when specifications overlap, only one of them will be utilized. For example, when addresses 7F00H to 7FFFH for CS0 are specified at the same time as 880H to 7FFFH for CS1, only the CS0 setting and pin will be active.) Note 3: When the bus is released ( BUSAK = "0"), the CS0 to CS2 pins are also released (the output buffer is OFF). For further information about the state of pins, refer to the note about the bus release in section 3.5 "Functions of Ports". 93CS40-92 20004-02-10 TMP93CS40/TMP93CS41 3.6.5 Example of Usage (1) Example of usage -1 Figure 3.6.1 is an example in which an external memory is connected to the TMP93CS41. In this example, a ROM is connected using a 16-bit bus; a RAM is connected using an 8-bit bus. 74HC573 D TMP93CS41 CS0 CS1 CS2 Q LE CS Address Bus D LE Q Upper byte ROM CS Lower byte ROM CS 8-bit bus RAM CS 8-bit bus I/O OE OE OE WE OE WE ALE AD8 to AD15 EA AD0 to AD7 AM8/ AM16 RD WR Figure 3.6.1 Example of External Memory Connection (ROM = 16 bits, RAM and I/O = 8 bits) Resetting sets pins CS0 to CS2 to input port mode. CS0 and CS1 are set high due to an internal pull-up resistor; CS2 is set low due to an internal pull-down resistor. The program used to set these pins is as follows. P4CR P4FC B0CS B1CS B2CS LD LD LD LD LD EQU 0EH EQU 10H EQU 68H EQU 69H EQU 6AH (B0CS), 1X010000B (B1CS), 1X011100B (B2CS), 1X000100B (P4CR), XXXXX111B (P4FC), XXXXX111B ; CS0 = 8 bits, 2 waits, 7F00H to 7FFFH ; CS1 = 8 bits, 0 waits, 880H to 7EFFH ; CS2 = 16 bits, 1 wait, 8000H to 3FFFFFH CS0 , CS1 , CS2 output mode setting X: Don't care 93CS40-93 20004-02-10 TMP93CS40/TMP93CS41 (2) Example of usage -2 Figure 3.6.2 is an example in which an external memory is connected to the TMP93CS41. In this example, a ROM, RAM, and I/O are each connected using an 8-bit bus. Address bus TMP93CS41 CS0 CS1 CS2 74HC573 CS D LE Q OE 8-bit bus ROM CS 8-bit bus RAM CS 8-bit bus I/O OE WE OE WE ALE A8 to A15 EA AD0 to AD7 RD WR AM8/ AM16 Figure 3.6.2 Example of External Memory Connection (ROM, RAM and I/O = 8 Bits) Resetting sets pins CS0 to CS2 to input port mode. CS0 and CS1 are set high due to an internal pull-up resistor; CS2 is set low due to an internal pull-down resistor. The program used to set these pins is as follows. P4CR P4FC B0CS B1CS B2CS LD LD LD LD LD EQU 0EH EQU 10H EQU 68H EQU 69H EQU 6AH (B0CS), 1X010000B (B1CS), 1X011100B (B2CS), 1X000100B (P4CR), XXXXX111B (P4FC), XXXXX111B ; CS0 = 8 bits, 2 waits, 7F00H to 7FFFH ; CS1 = 8 bits, 0 waits, 880H to 7EFFH ; CS2 = 8 bits, 1 wait, 8000H to 3FFFFFH CS0 , CS1 , CS2 output mode setting X: Don't care 93CS40-94 20004-02-10 TMP93CS40/TMP93CS41 (3) Example of usage -3 Figure 3.6.3 is an example in which an external memory is connected to the TMP93CS40. In this example, a 128-Kbyte ROM is connected using a 16-bit bus, and a 256-Kbyte RAM is connected using a 16-bit bus. TMP93CS40 A16 to A17 AD8 to AD15 Latch x 16 D Q LE A16 A1 to A15 ROM (128 Kbits x 16) A15 A0 to A14 OE CE D8 to D15 D0 to D7 AD0 to AD7 ALE CS2 RAM (128 Kbits x 8) A16 to A17 A1 to A15 A15 to A16 A0 to A14 OE I/O1 to 8 RD HWR R/ W CE 1 Upper byte CS1 WR RAM (128 Kbits x 8) A16 to A17 A1 to A15 A15 to A16 A0 to A14 OE R/ W CE 1 I/O1 to 8 AM8/ AM16 EA Lower byte Figure 3.6.3 Example of External Memory Connection (ROM & RAM = 16 bits) The TMP93CS40 has built-in ROM and RAM. When ROM and RAM have insufficient capacity, it is possible to connect an external memory following the usage examples for this purpose. In this example, the memory configuration is as follows. Memory ROM SRAM Internal External Internal External Memory Size 64 Kbytes 128 Kbytes 2 Kbytes 256 Kbytes Address 008000H to 017FFFH 400000H to 41FFFFH 000080H to 00087FH 800000H to 83FFFFH CS Pin - CS2 Data Bus 16 bits 16 bits 16 bits 16 bits - CS2 93CS40-95 20004-02-10 TMP93CS40/TMP93CS41 3.7 8-Bit Timers The TMP93CS40 and S41 contain two 8-bit timers (Timers 0 and 1), each of which can be operated independently. The cascade connection also allows these timers to be used together as a 16-bit timer. The following four operating modes are supported for the 8-bit timers: * * * * 8-bit interval timer mode (2 timers) 16-bit interval timer mode (1 timer) 8-bit programmable square wave pulse generation (PPG: Variable duty with variable cycle) output mode (1 timer) 8-bit pulse width modulation (PWM: Variable duty with constant cycle) output mode (1 timer) Figure 3.7.1 shows the block diagram of the 8-bit timers (Timer 0 and timer 1). Each timer consists of an 8-bit up counter, 8-bit comparator, and 8-bit timer register. Besides, one timer flip-flop (TFF1) is provided for the pair consisting of timer 0 and timer 1. Among the input clock sources for the timers, the internal clocks of T1, T4, T16, and T256 are obtained from the 9-bit prescaler shown in Figure 3.7.2. The operation modes and timer flip-flops of the 8-bit timers are controlled by the three control registers TMOD, TFFCR, and TRUN. 93CS40-96 20004-02-10 TRUN TRUN Timer F/F Run Run Clear Clear control TFF1 TO1 (also used as P71) Selector 2n - 1 Overflow T1 T16 T256 Selector TMOD TI0 pin T1 T4 T16 8-bit up counter (UC0) 8-bit up counter (UC1) TFFCR, TMOD TMOD Figure 3.7.1 Block Diagram of 8-Bit Timers (Timers 0 and 1) 93CS40-97 8-bit comparator (CP0) 8-bit comparator (CP1) Select 8-bit timer register TREG0 Register buffer TFFCR Match detection Selector TMOD PPGTRG PWMTRG TREG0-WR INTT1 TMP93CS40/TMP93CS41 20004-02-10 TMP93CS40/TMP93CS41 1. Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock signals for the 8-bit timers 0 and 1, the 16-bit timers 4 and 5, and the serial interfaces 0 and 1. Figure 3.7.2 shows the corresponding block diagram, and Table 3.7.1 shows prescaler clock signal resolution into 8 and 16-bit timers. To CPU System clock (fSYS) To 5-bit prescaler 9-bit prescaler 2 fFPH Selector 2 4 8 16 32 64 128 256 512 2 4 T1 T4 T16 T256 T1 T4 T16 To 8-bit timers 0 and 1 SYSCR0 Selector XT1 fs Run/stop and clear TRUN To 16-bit timers 4 and 5 SYSCR1 1 T0 T2 T8 T32 Selector To serial interfaces 0 and 1 fc fc/2 fc/4 fc/8 fc/16 SYSCR1 /2 /4 /8 /16 Figure 3.7.2 Block Diagram of the Prescaler Table 3.7.1 Prescaler Clock Resolution to 8 and 16-Bit Timers at fc = 20 MHz, fs = 32.768 kHz Select System Clock 3 4 5 6 7 Prescaler Clock Resolution T1 (244 s) (0.4 s) (0.8 s) (1.6 s) (3.2 s) (6.4 s) (244 s) (6.4 s) fs/25 fc/2 fc/2 fc/2 fc/2 fc/2 5 6 7 8 9 T4 (977 s) (1.6 s) (3.2 s) (6.4 s) (12.8 s) (25.6 s) (977 s) (25.6 s) 16-bit timer 8-bit timer fs/27 fc/2 fc/2 fc/2 fc/2 fc/2 7 8 9 10 11 T16 (3.9 ms) (6.4 s) (12.8 s) (25.6 s) (51.2 s) (102.4 s) (3.9 ms) T256 fs/211 (62.5 ms) fc/211 (102.4 s) fc/212 (204.8 s) fc/213 (409.6 s) fc/214 (0.82 ms) fc/215 (1.64 ms) fs/211 (62.5 ms) fc/215 (1.64 ms) XXX 000 (fc) 001 (fc/2) 010 (fc/4) 011(fc/8) 100 (fc/16) 01 (Low-frequency clock) XXX XXX XXX: Don't care XXX XXX fs/23 fc/27 fs/25 fc/29 fs/27 10 (Note) (fc/16 clock) fc/211 (102.4 s) Note: The fc/16 clock cannot be used as a prescaler clock when the fs is used as a system clock. 93CS40-98 20004-02-10 TMP93CS40/TMP93CS41 The timer clock selected among fFPH, fc/16, and fs is divided by 4 and input to this prescaler. The selection is made by system clock control register SYSCR0 93CS40-99 20004-02-10 TMP93CS40/TMP93CS41 3. Timer registers These are 8-bit registers for setting a time interval. When the values of the timer registers match the values of the corresponding up counters, the comparator match detect signal becomes active. If the set value is 00H, this signal becomes active when the up counter overflows. Timer register TREG0 has a double buffer. The timer flip-flop control register TFFCR Up counter Comparator (CP0) Timer register 0 (TREG0) Matching detection of PPG cycle 2n - 1 overflow of PWM TREG0 WR Shift trigger Register buffer 0 Write Internal data bus Selector TFFCR Figure 3.7.3 Configuration of Timer Register 0 Note: The timer register and the register buffer are allocated at the same memory address. When The memory address of each timer register is as follows. TREG0: 000022H TREG1: 000023H Both of these registers are write-only and cannot be read. 93CS40-100 20004-02-10 TMP93CS40/TMP93CS41 4. Comparator A comparator compares the value in the up counter with the values to which the timer register is set. When they match, the up counter is cleared to zero and an interrupt signal (INTT0 and INTT1) is generated. If the timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. 5. Timer flip-flop The timer flip-flop (TFF1) is a flip-flop inverted by the match detect signal (8-bit comparator output). Inverting is enabled or disabled by the timer flip-flop control register TFFCR 93CS40-101 20004-02-10 TMP93CS40/TMP93CS41 7 TRUN (0020H) Bit symbol Read/Write After reset Function PRRUN R/W 0 6 5 T5RUN 0 4 T4RUN 0 3 P1RUN R/W 0 2 P0RUN 0 1 T1RUN 0 0 T0RUN 0 Prescaler and timer run/stop control 0: Stop and clear 1: Run (Count up) Count operation 0 1 Stop and clear Count PRRUN: Operation of prescaler T5RUN: Operation of 16-bit timer (Timer 5) T4RUN: Operation of 16-bit timer (Timer 4) P1RUN: Operation of PWM timer (PWM1/timer 3) P0RUN: Operation of PWM timer (PWM0/timer 2) Note: TRUN 7 SYSCR0 Bit symbol (006EH) Read/Write After reset Function Highfrequency oscillator (fc) 0: Stop 6 XTEN 0 Lowfrequency oscillator (fs) 0: Stop High- 5 RXEN 1 Lowfrequency 4 RXTEN 0 Clock frequency 3 RSYSCK R/W 0 selection timer 2 WUEF 0 Warm-up 1 PRCK1 0 00: fFPH 01: fs 0 PRCK0 0 XEN 1 Select prescaler clock oscillator (fc) oscillator (fs) after release (Write) after release of after release of the STOP 0: Don't care 10: fc/16 of the STOP mode mode 0: Stop 1: Oscillation 0: fc 1: fs 1: Start timer 11: (Reserved) (Read) 0: End warm up 1: Continue warm up 1: Oscillation 1: Oscillation the STOP mode 0: Stop 1: Oscillation Select prescaler clock setting 00 fFPH 01 fs 10 fc/16 11 (Reserved) Clock divided by 4 Figure 3.7.4 Timer Operation Control Register/System Clock Control Register 93CS40-102 20004-02-10 TMP93CS40/TMP93CS41 7 TMOD (0024H) Bit symbol Read/Write After reset Prohibit readmodifywrite Function 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM T10M1 6 T10M0 0 5 PWMM1 0 PWM cycle 00: - 01: 26 - 1 10: 27 - 1 11: 28 - 1 4 PWMM0 W 0 3 T1CLK1 0 00: TO0TRG 01: T1 10: T16 11: T256 2 T1CLK0 0 1 T0CLK1 0 00: TI0 pin input 01: T1 10: T4 11: T16 0 T0CLK0 0 Source clock of timer 1 Source clock of timer 0 Input clock signal of timer 0 00 01 10 11 External input (TI0 pin input) T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) Input clock of timer 1 TMOD 00 01 10 11 Comparator output of timer 0 Internal clock T1 Internal clock T16 Internal clock T256 Overflow output of timer 0 (16-bit timer mode) Select PWM cycle 00 01 10 11 - 26 - 1 27 - 1 28 - 1 Set the operation modes of timers 0 and 1. 00 01 10 11 Two 8-bit timers (Timer 0 and timer 1) 16-bit timer 8-bit PPG output 8-bit PWM output (Timer 0) 8-bit timer (Timer 1) Figure 3.7.5 Timer Mode Control Register (TMOD) 93CS40-103 20004-02-10 TMP93CS40/TMP93CS41 7 TFFCR (0025H) Bit symbol Read/Write After reset Function 6 5 4 DBEN R/W 0 Double buffer 0: Disable 1: Enable 3 TFF1C1 W 1 00: Invert TFF1 01: Set TFF1 10: Clear TFF1 11: Don't care 2 TFF1C0 1 1 TFF1IE R/W 0 TFF1 inversion trigger 0: Disable 1: Enable 0 TFF1IS 0 TFF1 inversion source 0: Timer 0 1: Timer 1 Select inverse signal of timer F/F1 ("Don't care" except in 8-bit timer mode) TMOD 00 01 16-bit timer Inversion by match signal 10 PPG mode Inversion by matching signals of both timer 0 and timer 1 11 PWM mode Inversion by matching and overflow signals of timer 0 Inversion by 0 signal Inversion by 1 timer 1 match signal Inversion of timer flip-flop 1 (TFF1) 0 1 Disable inversion Enable inversion timer 0 match mode Control of timer flip-flop 1 (TFF1) Invert the value of TFF1 00 (Software inversion) 01 10 11 Set TFF1 to "1". Clear TFF1 to "0". Don't care Double buffer control of TREG0 0 1 Note: TFFCR Figure 3.7.6 Timer Flip-Flop Control Register (TFFCR) 93CS40-104 20004-02-10 TMP93CS40/TMP93CS41 The operation of 8-bit timers will be described below: (1) 8-bit timer mode Two interval timers, designated "0" and "1", can be used independently as 8-bit interval timers. All interval timers operate in the same manner, and thus only the operation of timer 1 will be explained below. 1. Generating interrupts in a fixed cycle To generate timer 1 interrupts at constant intervals using timer 1 (INTT1), first stop timer 1. Set the operation mode and input clock speed by setting TMOD, and the cycle time by setting TREG1. Then, enable interrupt INTT1 and start the counting of timer 1. Example: To generate timer 1 interrupt every 1 second at fs = 32 kHz, set each register in the following manner. Clock condition System clock: Low frequency (fs) Prescaler clock: Low frequency (fs) MSB 7 TRUN TMOD TREG1 INTET10 TRUN 6 X 0 1 1 X 5 4 3 2 1 0 LSB 0 - 0 1 1 1 - X 1 0 - X 1 1 - 1 1 - 0 0 - 1 - - 0 Stop timer 1, and clear it to "0". Set the 8-bit timer mode, and select T16 (4 ms at fs = 32 kHz) as the input clock. Set the timer register 1, 1 s / T16 = 250 = FAH (H signifies hexadecimal). Enable INTT1, and set it to "Level 5". Start timer 1 counting. - - - - - - - 1 - - X: Don't care, -: No change Use Table 3.7.1 for selecting the input clock. Note: The input clock choices available for timer 0 and timer 1 differ from each other as follows. Timer 0: TI0 input, T1, T4, T16 Timer 1: Match detect signal of timer 0, T1, T16, T256 93CS40-105 20004-02-10 TMP93CS40/TMP93CS41 2. Generating a 50% duty, square-wave pulse The timer flip-flop (TFF1) is inverted at constant intervals, and its status is output to timer output pin (TO1). Example: To output a 2.4 s square wave pulse from the TO1 pin at fc = 20 MHz, set each register by the following procedures. Either timer 0 or timer 1 may be used, but this example uses timer 1. * Clock condition System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH 7 - 0 6 X 0 0 - X X X 5 - X 0 - X X - 4 - X 0 - X X - 3 - 0 0 1 2 - 1 0 0 1 0 - 1 1 1 1 1 0 - - 1 1 TRUN TMOD TREG1 TFFCR P7CR P7FC TRUN Stop timer 1, and clear it to "0". Set the 8-bit timer mode, and select T1 (0.4 s at fc = 20 MHz) as the input clock cycle time. Set the timer register at 2.4 s / T1 / 2 = 3. Clear TFF1 to "0", and set to invert by the match detect signal from timer 1. 0 - X X 1 - - - - - - - X - Select P71 as TO1 pin. Start timer 1 counting. X: Don't care, -: No change T1 TRUN TFF1 TO1 1.2 s at fc = 20 MHz Figure 3.7.7 Square Wave (50% duty) Output Timing Chart 93CS40-106 20004-02-10 TMP93CS40/TMP93CS41 3. Making timer 1 count up by matching the signal from the timer 0 comparator Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1. Comparator output (Timer 0 match) Timer 0 up counter (when TREG0 = 5) Timer 1 up counter (when TREG1 = 2) Timer 1 matching output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.8 Timer 1 Count Up Regulated by Timer 0 (2) 16-bit timer mode A 16-bit interval timer is configured by using timer 0 and timer 1 as a pair. Setting timer mode register TMOD High frequency (fc) 1 (fc) fFPH When counting with the T16 input clock (6.4 s at 20 MHz) 0.4 s / 6.4 s = 62500 = F424H Therefore, set TREG1 = F4H and TREG0 = 24H, respectively. 93CS40-107 20004-02-10 TMP93CS40/TMP93CS41 The comparator signal is output from timer 0 each time the up counter UC0 matches TREG0, when the up counter UC0 is not to be cleared. With the timer 1 comparator, the match detect signal is output at each comparator check when the up counter UC1 and TREG1 values are found to match. When the match detect signal is output simultaneously from the comparators of both timer 0 and timer 1, the up counters UC0 and UC1 are cleared to 0, and the interrupt INTT1 is generated. If inversion is enabled, the value of the timer flip-flop TFF1 is inverted. Example: When TREG1 = 04H and TREG0 = 80H 0000H 0080H 0180H 0280H 0380H 0480H Value of up counter (UC1, UC0) Timer 0 comparator match detect signal Interrupt INTT1 Timer output TO1 Inversion Figure 3.7.9 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulse can be generated at any frequency and duty by timer 0. The output pulse may be either low-active or high-active. In this mode, timer 1 cannot be used. Timer 0 outputs a pulse to the TO1 pin (also used as P71). tH tL t TREG0 and UC0 match (Interrupt INTT0) TREG1 and UC0 match (Interrupt INTT1) TO1 TREG0 TREG1 Figure 3.7.10 8-Bit PPG Output Waveforms 93CS40-108 20004-02-10 TMP93CS40/TMP93CS41 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the timer registers TREG0 and TREG1. However, it is necessary for the set value of TREG0 to be smaller than that of TREG1. Though the up counter (UC1) of timer 1 is not used in this mode, UC1 should be set for counting by setting TRUN TO1 TI0 pin T1 T4 T16 TRUN Inversion TMOD Comparator INTT1 TREG0 TREG0-WR Selector Shift trigger Register buffer TFFCR Figure 3.7.11 Block Diagram of 8-Bit PPG Output Mode When the double buffer of TREG0 is enabled in this mode, the value of the register buffer will be shifted in TREG0 each time TREG1 matches UC0. Use of the double buffer makes the handling of low duty waves easy (when duty is varied). Match with TREG0 and up counter 0 (Up counter = Q1) Match with TREG1 TREG0 (Value to be compared) Register buffer Shift from register buffer Q1 Q2 Q2 Q3 TREG 0 (Register buffer) write (Up counter = Q2) Figure 3.7.12 Operation of Register Buffer 93CS40-109 20004-02-10 TMP93CS40/TMP93CS41 Example: Generating 1/4 duty 62.5 kHz pulse (at fc = 20 MHz) 16 s Clock condition System clock: Clock gear: Prescaler clock: * High frequency (fc) 1 (fc) fFPH Calculate the value to be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle time t should be: t = 1/62.5 kHz = 16 s. Given T1 = 0.4 s (at 20 MHz), 16 s / 0.4 s = 40 Consequently, set the timer register 1 (TREG1) to TREG1 = 40 = 28H and then to obtain a duty of 1/4, t x 1/4 = 16 s x 1/4 = 4 s 4 s / 0.4 s = 10 Therefore, set timer register 0 (TREG0) to TREG0 = 10 = 0AH. 7 - 1 0 0 - 6 X 0 0 0 - 5 - X 0 1 - 4 - X 0 0 X 3 - X 1 1 0 2 - X 0 0 1 1 0 0 1 0 1 0 0 1 0 0 X Stop timers 0 and 1, and clear then. Set the 8-bit PPG mode, and select T1 as input clock. Write "0AH". Write "28H". Set TFF1 and enable the inversion. Writing "10" provides negative logic pulse. P7CR P7FC TRUN TRUN TMOD TREG0 TREG1 TFFCR X X 1 X X X X X - X X - - - - - - - 1 1 1 - X 1 Set P71 as the TO1 pin. Start timer 0 and timer 1 counting. X: Don't care, -: No change 93CS40-110 20004-02-10 TMP93CS40/TMP93CS41 (4) 8-bit PWM output mode This mode is valid only for timer 0. In this mode, the maximum 8-bit resolution of the PWM pulse can be output. The PWM pulse is output to the TO1 pin (also used as P71) when using timer 0. Timer 1 can also be used as an 8-bit timer. Timer output is inverted when the up counter (UC0) matches the set value of timer register TREG0, or when 2n - 1 (n = 6, 7, or 8; specified by TMOD TREG0 and UC0 match 2n - 1 overflow (Interrupt INTT0) TO1 tPWM (PWM cycle) Figure 3.7.13 8-Bit PWM Waveforms Figure 3.7.14 shows the block diagram of operations in this mode. TRUN Selector Clear TMOD |